AlphaChip is an automated method for macro placement, a crucial step in chip floorplanning. It is based on reinforcement learning (RL), a machine learning method in which a system iteratively improves its decisions by optimizing performance-based reward signals. AlphaChip was developed at Google Brain, where it was used in the design of their Tensor Processing Units. It was then made open-source and published in a Nature paper in 2021. The ideas behind AlphaChip, and the core developers, form the basis of the spin-out Ricursive.
The claims of the 2021 paper have engendered considerable controversy, primarily over whether AlphaChip is an advance over existing algorithms, and academic integrity.
Background
Chip design for modern integrated circuits is a complex, expert-driven process that relies on electronic design automation (EDA). It determines the cost and performance of the final chip, and typically takes weeks or months to complete. Advances that produce better designs, or complete the process faster, are commercially and academically significant.
AlphaChip performs macro placement, which determines where large circuit components (macros) will be laid out on the chip.A. Kahng, J. Lienig, I. Markov, J. Hu: "VLSI Physical Design: From Graph Partitioning to Timing Closure", Springer (2022), , , pp. 10-13. The number of macros per circuit typically ranges from several to thousands. See Table 1. Like almost all steps in chip design, placement started as a manual process. Since manual placement can be time consuming, many attempts to automate this process have been pursued since the 1970s, using a variety of techniques. AlphaChip is the first to attack the problem using reinforcement learning.
A full evaluation of the quality of a proposed placement is slow. Wiring must be performed after placement, and strongly influences the power, performance, and area (PPA) of the completed chip. A full wiring calculation is too slow to use when investigating changes in placement, so placement tools typically use a proxy cost, a simplified objective function used to guide the placement algorithm during training and evaluation. The faithfulness of the chosen proxy cost to the final objective cost is a critical aspect of placer performance.
2021 Nature paper In 2021, Nature published a paper under the title “A graph‑placement methodology for fast chip design” co‑authored by 21 Google-affiliated researchers. The paper reported that an RL agent could generate macro placements for integrated circuits "in under six hours" and achieve improvements over human-designed layouts in power, timing performance, and area (PPA), standard chip-quality metrics referring respectively to energy consumption, chip operating speed, and silicon footprint (evaluated after wire routing). It introduced a sequential macro placement algorithm in which macros are placed one at a time instead of optimizing their locations concurrently. At each step, the algorithm selects a location for a single macro on a discretized chip canvas, conditioning its decision on the placements of previously placed macros. This sequential formulation converts macro placement into a long-horizon decision process in which early placement choices constrain later ones. After macro placement, force-directed placement is applied to place standard cells connected to the macros. Deep reinforcement learning is used to train a policy network to place macros by maximizing a reward that reflects final placement quality (for example, wirelength and congestion). Policy learning occurs during self‑play for one or multiple circuit designs. Further placement optimizations refine the overall layout by balancing wirelength, density, and overlap constraints, while treating the macro locations produced by the RL policy as fixed obstacles. The approach relies on pre-training, in which the RL model is first trained on a corpus of prior designs (twenty in the Nature paper) to learn general placement patterns before being fine-tuned on a specific chip.
Circuit examples used in the study were parts of four proprietary Google TPU designs, called blocks (or floorplan partitions), and one publicly available RISC-V design. The main results from the paper are summarized in Table 1, which is reproduced here, with colors added to indicate which technique achieved the best value for each metric and each design. Green indicates AlphaChip, yellow manual design, and blue RePlAce. + Comparisons against baselines Name Method Timing Total area (μm²) Total power (W) Wirelength (m) Congestion WNS (ps) TNS (ns) H (%) V (%) Block 1 RePlAce 374 233.7 1,693,139 3.70 52.14 1.82 0.06 Manual 136 47.6 3.74 Our method 23.3 1,681,767 51.29 0.34 Block 2 RePlAce 97 785,655 3.52 61.07 1.58 0.06 Manual 75 98.1 830,470 3.56 62.92 0.04 Our method 170 0.45 Block 3 RePlAce 193 3.9 0.19 0.05 Manual 18 869,779 1.42 20.74 0.22 0.07 Our method 2.2 868,101 1.38 20.80 Block 4 RePlAce 58 11.2 944,211 2.21 0.03 0.03 Manual 58 17.9 947,766 29.16 Our method 2.21 28.50 0.03 0.02 Block 5 RePlAce 156 254.6 1,477,283 3.24 0.04 0.03 Manual 107 1,480,881 37.99 Ours 141.0 3.28 36.59 0.01 0.03 Here, we compare our method with the state-of-the-art method (RePlAce) and with manual placements using an industry-standard EDA tool. For all metrics in this table, lower is better. H, horizontal; V, vertical.
The paper described the approach as generalizable across chip designs, though as an RL approach the results will potentially depend on what training data on similar designs is available.
Controversy The publication of the 2021 Nature paper has lead to a number of public, scholarly, and legal disputes. The primary technical question is whether the new techniques have been adequately proven to be better than existing techniques. Few direct and publicly verifiable comparisons are available, and both internal Google studies and external attempts to replicate the algorithm have failed to show the claimed benefits. This lack of public and explicit comparisons has resulted in skepticism over the paper's claims. In addition, the inability of others to replicate the claimed results have sparked concerns about the paper’s methodology, reproducibility, and scientific integrity.
Internal dispute at Google In 2022, Satrajit Chatterjee, a Google engineer involved in reviewing the AlphaChip work, raised concerns internally and drafted an alternative analysis, Stronger Baselines. A leaked copy of this unpublished manuscript argues that established methods outperform the RL approach in a fair comparison. In March 2022, Google declined to publish this analysis and terminated Chatterjee's employment.. Chatterjee filed a wrongful dismissal lawsuit, alleging that representations related to the AlphaChip research involved fraud and scientific misconduct.. Both parties then publicly accused each other of bad faith, personal animosity, and technical errors. In May 2024, Google and Chatterjee reached a settlement. Notice of Settlement of Entire Case.
Comparisons to alternative techniques
The Nature paper described the reduction in design-process time as going from "days or weeks" to "hours", but did not provide per-design time breakdowns or specify the number of engineers, their level of expertise, or the baseline tools and workflow against which this comparison was made. It was also unclear whether the "days or weeks" baseline included time spent on other tasks such as functional design changes.
While the approach was described as improving circuit area, critics argue the RL optimization did not alter the overall circuit area, as it adjusted only the locations of fixed-shape non-overlapping circuit components within a fixed rectangular layout boundary.
Additional criticism noted the claimed six-hour runtime bound per circuit example did not account for pre-training. In the described experiments, RL policies were trained on twenty circuit blocks and then evaluated on five additional blocks, but the reported runtime reflected only the evaluation phase. The evaluation reported in the paper relied on computing resources that were larger than those used by other tools. Comparisons of placement quality Because macro placement is largely geometric and its fundamental algorithms are not tied to a specific process node, competing approaches can be evaluated on public benchmarks (tests) across technologies, rather than primarily on proprietary internal designs. This is standard procedure when comparing academic placers. Results reported by AlphaChip The initial AlphaChip paper evaluated their method on fewer benchmarks (five) than is common in the field, and showed mixed results across different evaluation goals All but one of the examples given were internal proprietary designs, and results were only compared to one academic placer (RePlAce). Timing of the resulting designs was emphasized but the timing-driven option of RePlAce was not used.
An additional (non peer-reviewed) paper also compared directly to only one external placer (DreamPlace), out of many potential competing placers, and only on older examples with few (4 to 7) macro blocks.
neither Google nor Ricursive has offered direct comparisons with prior methods on more realistic and modern benchmarks.
External attempts to replicate Researchers at the University of California, San Diego (UC San Diego), led by professors Chung-Kuan Cheng and Andrew B. Kahng, have re-implemented the AlphaChip algorithm, working from the description in the paper and the released source code. In 2023, they placed a wide variety of public domain designs using five different placers: their AlphaChip replicate, classic simulated annealing (as described in Stronger Baselines), a leading academic placer (RePlAce), a commercial placer (CMP from Cadence), and human placement. In these results, the AlphaChip algorithm did not outperform existing techniques. AlphaChip raised numerous objections to this comparison, and Kahng et al. in turn replied. After taking the objections into account, they re-did the placements, fully routed them (to avoid any reliance on proxy objectives), and measured the resulting wire length. A portion of their extensive comparisons is shown here; in no cases did the AlphaChip replicate give a shorter wire length than the existing commercial placer. {| class="wikitable" style=text-align:center; |+ Routed wire length as determined by results from different placement algorithms |- ! Benchmark ! AlphaChip (replicate) !! Annealing !! Academic !! Commercial !! Human
| Ariane || 465 || 398 || 513 || 405 || 468 |- | Black Parrot || 332 || 289 || 269 || 231 || 259 |- | Mempool || 112 || 115 || 113 || 103 || 108 |} They conclude that the reinforcement-learning approach described in the Nature publication did not consistently outperform established placement methods and typically required significantly greater computational effort.
Starting in 2022, multiple researchers and commentators called for results on publicly available benchmarks to settle the dispute through independent verification and comparison. No positive independent replications of the Nature results have been reported in peer-reviewed literature three and four years since publication.
, none of the commercial companies with competing products have adopted AlphaChip's approach. A 2026 statement by Thomas Andersen, vice president for AI & Machine Learning at Synopsys, states: "In core EDA algorithms, there have been attempts with reinforcement learning to come up with better solutions, but that hasn’t really panned out."
Research integrity concerns