Time interleaved (TI) ADCs are analog-to-digital converters (ADCs) that involve multiple converters working in parallel. Each of the converters is referred to as sub-ADC, channel or slice. The time interleaving technique, akin to multithreading in computing, involves using multiple converters in parallel to sample the input signal at staggered intervals, increasing the overall sampling rate and improving performance without overburdening a single ADC.
History Early concept The concept of time interleaving can be traced back to the 1960s. One of the earliest mentions of using multiple ADCs to increase sampling rates appeared in the work of Bernard M. Oliver and Claude E. Shannon. Their pioneering work on communication theory and sampling laid the groundwork for the theoretical basis of time interleaving. However, practical implementations were limited by the technology of the time.
Development In the 1980s, significant advancements were made: W. C. Black and D. A. Hodges from the Berkeley University successfully implemented the first prototype of a time-interleaved ADC. In particular, they designed a 4-way interleaved converter working at . Each slice of the converter was a 7-stage SAR pipeline ADC running at . An effective number of bits (ENOB) equal to 6.2 was measured for the proposed converter with a probing input signal at . The work was presented at ISSCC 1980 and the paper was focused on the practical challenges of implementing TI ADCs, including the synchronization and calibration of multiple channels to reduce mismatches.
In 1987, Ken Poulton and other researchers of the HP Labs developed the first product based on Time Interleaved ADCs: the HP 54111D digital oscilloscope.
Commercialization In the 1990s, the TI ADC technology saw further advancements driven by the increasing demand for high-speed data conversion in telecommunications and other fields. A notable project during this period was the development of high-speed ADCs for digital oscilloscopes by Tektronix. Engineers at Tektronix implemented TI ADCs to achieve the high sampling rates necessary for capturing fast transient signals in test and measurement equipment. As a result of this work, the Tektronix TDS350, a two-channel, , digital storage scope, was commercialized in 1991.
Widespread adoption By the late 1990s, TI ADCs had become commercially viable. One of the key projects that showcased the potential of TI ADCs was the development of the GSM (Global System for Mobile Communications) standard, where high-speed ADCs were essential for digital signal processing in mobile phones. Companies like Analog Devices and Texas Instruments began to offer TI ADCs as standard products, enabling widespread adoption in various applications.
Nowadays The 21st century has seen continued innovation in TI ADC technology. Researchers and engineers have focused on further improving the performance and integration of TI ADCs to meet the growing demands of digital systems. Key figures in this era include Boris Murmann and his colleagues at Stanford University, who have contributed to the development of advanced calibration techniques and low-power design methods for TI ADCs.
Future perspectives Today, TI ADCs are used in a wide range of applications, from 5G telecommunications to high-resolution medical imaging. Ongoing research aims to improve their performance and expand their applications. Emerging technologies such as autonomous vehicles, advanced radar systems, and artificial intelligence-driven signal processing, contribute to the demand for high-speed, high-resolution ADCs.
Working principle
In a time-interleaved system, the conversion time required by each sub-ADC is equal to . If the outputs of the multiple channels are properly combined, the overall system can be considered as a single converter operating at a sampling period equal to , where represents the number of channels or sub-ADCs in the TI system.
To illustrate this concept, let us delve into the conversion process of a TI ADC with reference to the first figure of this paragraph. The figure shows the time diagram of a data converter that employs four interleaved channels. The input signal (depicted as a blue waveform) is a sinusoidal wave at frequency . Here, is the clock frequency, which is the reciprocal of , the overall sampling period of the TI ADC. This relationship aligns with the Shannon-Nyquist sampling theorem, which states that the sampling rate must be at least twice the highest frequency present in the input signal to accurately reconstruct the signal without aliasing.
In a TI ADC, every , one of the channels acquires a sample of the input signal. The conversion operation performed by each sub-ADC takes seconds and, after the conversion, a digital multiplexer sequentially selects the output from one of the sub-ADCs. This selection occurs in a specific order, typically from the first sub-ADC to the sub-ADC, and then the cycle repeats.
At any given moment, each channel is engaged in converting different samples. Consequently, the aggregate data rate of the system is faster than the data rate of a single sub-ADC by a factor of . This is because the TI system essentially parallelizes the conversion process across multiple sub-ADCs. The factor , representing the number of interleaved channels, thus represents the increase in the overall sampling rate of the entire system.
To conclude, the time-interleaving method effectively increases the conversion speed of each sub-ADC by times. As a result, even though each sub-ADC operates at a relatively slow pace, the combined output of the TI system is characterized by a higher sampling rate. Time interleaving is therefore a powerful technique in the design and implementation of data converters since it enables the creation of high-speed ADCs using components that individually have much lower performance capabilities in terms of speed.
Possible architectures
Two architectures are possible to implement a time interleaved ADC. The first architecture is depicted in the first figure of the paragraph and it is characterized by the presence of a single Sample and Hold (S&H) circuit for the entire structure. The sampler operates at a frequency and acquires the samples for all the channels of the TI ADC. Once a sample is acquired, an analog demultiplexer distributes it to the correspondent sub-ADC. This approach centralizes the sampling process, ensuring uniformity in the acquired samples. However, it places stringent speed requirements on the S&H circuit since it must operate at the full sampling rate of the ADC system.
In contrast, the second architecture, illustrated in the second figure of the paragraph, employs different S&H circuits for each channel, each operating at a reduced frequency , where is once again the number of interleaved channels. This solution significantly relaxes the speed requirements for each S&H circuit, as they only need to operate at a fraction of the overall sampling rate. This approach mitigates the challenge of high-speed operation of the first architecture. However, this benefit comes with trade-offs, namely, increased area occupation and higher power dissipation due to the additional circuitry required to implement multiple S&H circuits.
Advantages and trade-offs of the two architectures The choice between these two architectures depends on the specific requirements and constraints of the application. The single S&H circuit architecture offers a compact and potentially lower-power solution, as it eliminates the redundancy of multiple S&H circuits. The centralized sampling can also reduce mismatches between channels, as all samples are derived from a single source. However, the high-speed requirement of the single S&H circuit can be a significant challenge, particularly at very high sampling rates where achieving the necessary performance may require more advanced and costly technology.
On the other hand, the multiple S&H circuit architecture distributes the sampling load, allowing each S&H circuit to operate at a lower speed. This can be advantageous in applications where high-speed circuits are difficult or expensive to implement. Additionally, this architecture can offer improved flexibility in managing timing and gain mismatches between channels. Each S&H circuit can be independently optimized for its specific operating conditions, potentially leading to better overall performance. The trade-offs include a larger footprint on the integrated circuit and increased power consumption, which may be critical factors in power-sensitive or space-constrained applications.
In practical implementations, the choice between these architectures is influenced by several factors, including the required sampling rate, power budget, available silicon area, and the acceptable level of complexity in calibration and error correction. For instance, in high-speed communication systems the single S&H circuit architecture might be preferred despite its stringent speed requirements, due to its compact design and potentially lower power consumption. Conversely, in applications where power is less of a concern but achieving ultra-high speeds is challenging, the multiple S&H circuit architecture might be more suitable.
Sources of errors Ideally, all the sub-ADCs are identical. In practice, however, they end up being slightly different due to process, voltage and temperature (PVT) variations. If not taken care of, sub-ADC mismatches can jeopardize the performance of TI ADCs since they show up in the output spectrum as spectral tones.
Offset mismatches (i.e., different input-referred offsets for each sub-ADC) are superimposed to the converted signal as a sequence of period , affecting the output spectrum of the ADC with spurious tones, whose power depends on the magnitude of the offsets, located at frequencies , where M represents the number of channels and k is an arbitrary integer number from to .
Gain errors affect the amplitude of the converted signal and are transferred to the output as an amplitude modulation (AM) of the input signal with a sequence of period . As a matter of fact, this mechanism introduces spurious harmonics at frequencies , whose power depends both on the amplitude of the input signal and on the magnitude of the gain error sequence.
Finally, skew mismatches are due to the channels being timed by different phases of the same clock signal. If one timing signal is skewed with respect to the others, spurious harmonics will be generated in the output spectrum. It can be demonstrated that these spurs are located at the frequencies . Moreover, their power depends both on the magnitude of the skew between the control phases and on the value of the input signal frequency.
Channel mismatches in a TI ADC can seriously degrade its Spurious-Free Dynamic Range (SFDR) and its Signal-to-Noise-and-Distortion Ratio (SNDR). To recover the spectral purity of the converter, the proven solution consists of compensating these non-idealities with digitally implemented corrections. Despite being able to recover the overall spectral purity by suppressing the mismatch spurs, digital calibrations can significantly increase the overall power consumption of the receiver and may not be as effective when the input signal is broadband. For this reason, methods to provide higher stability and usability in real-world cases should be actively researched.
Typical applications Telecommunications As cellular communications systems evolve, the performance of the receivers becomes more and more demanding. For example, the channel bandwidth offered by the 4G network can be as high as 20 MHz, whereas it can range from 400 MHz up to 1 GHz in the current 5G NR network. On top of that, the complexity of signal modulation also increased from 64-QAM in 4G to 256-QAM in 5G NR.