z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers. IBM introduced its first z/Architecture-based system, the z900, in late 2000. Subsequent z/Architecture systems include the IBM z800, z990, z890, System z9, System z10, zEnterprise 196, zEnterprise 114, zEC12, zBC12, z13, z14, z15, z16, and z17.
z/Architecture retains backward compatibility with previous 32-bit-data/31-bit-addressing architecture ESA/390 and its predecessors back to the 32-bit-data/24-bit-addressing System/360. The IBM z13 is the last z Systems server to support running an operating system in ESA/390 architecture mode. However, all 24-bit and 31-bit problem-state application programs originally written to run on the ESA/390 architecture will be unaffected by this change.
Features
z/Architecture includes almost all of the features of ESA/390, and adds some new features. Among the features of z/Architecture are
A channel subsystem with the architecture introduced by S/370-XA Branch relative instructions introduced by ESA/390, with 16-bit signed halfword offsets Relative long instructions, with 32-bit signed halfword offsets Trimodal (24/31/64-bit) addresses 16 32-bit access registers (ARs) introduced by ESA/370 16 64-bit general registers (GRs), 32-bit on older architectures 16 64-bit control registers (CRs) introduced by System/370 as 32-bit 16 64-bit floating-point registers (FPRs) 32 128-bit vector registers (VRs); bits 0–63 of VR0–VR15 contain FPR0–FPR15 1 32-bit floating-point control (FPC) register 1 128-bit program-status word (PSW), which includes a 64-bit instruction address An 8-KiB prefix storage area (PSA) Cryptographic Facility IEEE Binary-floating-point instructions added by ESA/390 IEEE Decimal-floating-point instructions For information on when each feature was introduced, consult the Principles of Operation.
Extended-immediate facility The extended-immediate facility adds instructions with 32-bit signed and unsigned immediate operands, Find Leftmost ones, and miscellaneous load instructions, e.g., Load and test, Load byte, Load logical character.
General-instructions-extension facility The general-instructions-extension facility add 3 dozen instructions, including Compare and branch instructions Compare and trap instructions Load instructions, e.g. Load and test (LT) Store instructions
High-word facility The high-word facility provides instructions operating on the high word of a 64-bit general register.
Long-displacement facility The long-displacement facility adds instructions with a 20-bit signed displacement, e.g., LAY.
Miscellaneous-instruction-extensions Facility 1 The miscellaneous-instruction-extensions Facility 1 adds Compare logical and trap (CLT and CLGT) Rotate then insert selected bits (RISBGN)
Miscellaneous-instruction-extensions Facility 2 The miscellaneous-instruction-extensions Facility 2 adds Branch indirect on condition (BIC) new add, multiply and subtract instructions
Miscellaneous-instruction-extensions Facility 3 The miscellaneous-instruction-extensions Facility 3 And with complement (NCRK, NCGRK) Move right to left (MVCRL) Not and (NNRK, NNGRK) Not exclusive or (NXRK, NXGRK) Not or (NORK, NOGRK) Or with complement (OCRK, OCGRK) Select (SELR, SELGR) Select high (SELFHR)
Vector facility
The z13 introduced a 128-bit Packed SIMD facility named "Vector Facility", which was first documented in edition 11 of z/Architecture Principles of Operation. It adds 32 vector registers, each 128 bits wide; the existing 16 floating-point registers are overlaid on the new vector registers. The new architecture adds over 150 new instructions to operate on data in vector registers, including integer, floating-point, and string data types. The z13 implementation includes two independent SIMD units to operate on vector data. The older vector processor facility first introduced from the IBM 3090 and also supported in the ES/9000 is not supported in z/Architecture.
Neural-network-processing-assist facility The z16 introduced the Neural-network-processing-assist facility, which introduces several instructions performing operations on model-dependent data types. For the z16 this is the 16-bit NNP-Data-Type-1 Format.
The new instructions include tensor operations useful for AI and neural network applications.
Registers
IBM z/Architecture registers+ General Registers 0–15 Two's complement value 0 31 Two's complement value (continued) 32 63+ Access Registers 0–15 0 0 0 0 0 0 0 P ALESN ALEN 0 6 7 8 15 16 31+ Bits Field Meaning 0–6 0000000 7 P Primary0=use dispatchable-unit access list1=use primary-space access list 8–15 ALESN access-list-entry sequence number 16–31 ALEN access-list-entry number+ Breaking-event-address register (BEAR) See Principles of Operation 0 31 (continued) 32 63+ Control Registers 0–15 See Principles of Operation or Control Registers 0 31 (continued) 32 63+ Floating-Point Registers (hexadecimal) 0–15 S Biased exponent Mantissa 0 1 7 8 31 Mantissa (continued) 32 63+ Floating-Point Registers (binary, single precision) 0–15 S Biased exponent Mantissa 0 1 8 9 31+ Floating-Point Registers (binary, double precision) 0–15 S Biased exponent Mantissa 0 1 11 12 31 Mantissa (continued) 32 63+ Prefix register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 Prefix Bits 33–50 0 n/a 32 33 50 51 52 63+ z/Architecture long PSW 0 R 0 0 0 T IO EX Key 0 M W P AS CC ProgramMask RI 0 0 0 0 0 0 EA 0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 30 31 BA 0 32 33 63 Instruction Address 64 95 Instruction Address (Continued) 96 127+ Bits Field Meaning 1 R PER Mask 5 T DAT mode 6 IO I/O mask 7 EX External Mask 8–11 Key PSW key 12 E=0 Must be zero for LPSWE 13 M Machine-check mask 14 W Wait state 15 P Problem state 16–17 AS Address-Space Control00=primary-space mode01=Access-register mode10=Secondary-space mode11=Home-space mode 18–19 CC Condition Code 20–23 PM Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 HFP Exponent underflow 23 HFP Significance 24 RI Reserved for IBM 31 EA Extended Addressing mode0=defined by BA below; 1=64-bit, BA must be zero 32 BA Basic Addressing mode0=24 or 64; 1=31 64–127 IA Instruction Address+ z/Architecture short PSW 0 R 0 0 0 T IO EX Key 1 M W P AS CC ProgramMask RI 0 0 0 0 0 0 EA 0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 25 30 31 BA Instruction Address 32 33 63+ Bits Field Meaning 1 R PER Mask 5 T DAT mode 6 IO I/O mask 7 EX External Mask 8–11 Key PSW key 12 E=1 Must be one for LPSW 13 M Machine-check mask 14 W Wait state 15 P Problem state 16–17 AS Address-Space Control00=primary-space mode01=Access-register mode10=Secondary-space mode11=Home-space mode 18–19 CC Condition Code 20–23 PM Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 HFP Exponent underflow 23 HFP Significance 24 RI Reserved for IBM 31 EA Extended Addressing mode0=defined by BA below; 1=64-bit, BA must be zero 32 BA Basic Addressing mode0=24 or 64; 1=31 33–63 IA Instruction Address
Each processor has these registers
Access registers Breaking-event-address register (BEAR) Control registers Floating-point Control (FPC) register Floating-point registers General registers Prefix register Program status word (PSW) Vector registers
Access registers Each CPU has 16 32-bit access registers. When a program running in AR mode specifies register 1–15 as a base register or as a register operand containing an address, the CPU uses the associated access register during address translation.
Breaking-event-address register (BEAR) The 64-bit BEAR contains the address of the last instruction that broke the sequential execution of instructions; an interrupt stores the BEAR in the doubleword at real address 272 (). After an Execute of a branch, the BEAR contains the address of the execute, not that of the branch.
Control registers The 16 64-bit control registers provide controls over and the status of a CPU, except for information included in the PSW. They are an evolutionary enhancement to the control registers on the earlier ESA/390 on the IBM S/390 processors. For details on which fields are dependent on specific features, consult the Principles of Operation. Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390.
+ z/Architecture mode control registers CR bits Field 0 8 Transactional-execution control 0 9 Transactional-execution program-interruption filtering override 0 10 Clock-comparator sign control 0 13 Cryptography counter control 0 14 Processor-activity-instrumentation-extension control 0 15 Measurement-counter-extraction-authorization control 0 30 Warning-track subclass mask 0 32 TRACE TOD-clock control 0 33 SSM-suppression 0 34 TOD-clock-sync control 0 35 Low-address-protection control 0 36 Extraction-authority control 0 37 Secondary-space control 0 38 Fetch-protection-override control 0 39 Storage-protection-override control 0 40 Enhanced-DAT-enablement control 0 43 Instruction-execution-protection-enablement control 0 44 ASN-and-LX-reuse control 0 45 AFP-register control 0 46 Vector enablement control 0 48 Malfunction-alert subclass mask 0 48 Malfunction-alert subclass mask 0 49 Emergency-signal subclass mask 0 50 External-call subclass mask 0 52 Clock-comparator subclass mask 0 53 CPU-timer subclass mask 0 54 Service-signal subclass mask 0 56 Initialized to 1 0 57 Interrupt-key subclass mask 0 58 Measurement-alert subclass mask 0 59 Timing-alert subclass mask 0 61 Crypto control 1 0–51 Primary Address-Space Control Element (ASCE)Primary region-table originPrimary segment-table originPrimary real-space token origin 1 54 Primary subspace-group control 1 55 Primary private-space control 1 56 Primary storage-alteration-event 1 57 Primary space-switch-event control 1 58 Primary real-space control 1 60–61 Primary designation-type control 1 62–63 Primary table length 2 33–57 Dispatchable-unit-control-table origin 2 59 Guarded-storage-facility enablement control 2 61 Transaction diagnostic scope 2 62–63 Transaction diagnostic control 3 0–31 Secondary ASN-second-table-entry instance number 3 32–47 PSW-key mask 3 48–63 Secondary ASN 4 0–31 Primary ASN-second-table-entry instance number 4 32–47 Authorization index 4 48–63 Primary ASN 5 33–57 Primary-ASN-second-table-entry origin 6 32–39 I/O-interruption subclass mask 7 0–51 Secondary Address-Space Control Element (ASCE)Secondary region-table originSecondary segment-table originSecondary real-space token origin 7 54 Secondary subspace-group control 7 55 Secondary private-space control 7 56 Secondary storage-alteration-event control 7 58 Secondary real-space control 7 60–61 Secondary designation-type control 7 62–63 Secondary table length 8 16–31 Enhanced-monitor masks 8 32–47 Extended authorization index 8 48–63 Monitor masks 9 32 Successful-branching-event mask 9 33 Instruction-fetching-event mask 9 34 Storage-alteration-event mask 9 35 Storage-key-alteration-event mask 9 36 Store-using-real-address-event mask 9 37 Zero-address-detection-event mask 9 38 Transaction-end event mask 9 39 Instruction-fetching-nullification-event mask 9 40 Branch-address control 9 41 PER-event-suppression control 9 43 Storage-alteration-space control 10 0–63 PER starting address 11 0–63 PER ending address 12 0 Branch-trace control 12 1 Mode-trace control 12 2–61 Trace-entry address 12 62 ASN-trace control 12 63 Explicit-trace control 13 0–51 Home Address-Space Control Element (ASCE)Home region-table originHome segment-table originHome real-space token origin 13 55 Home private-space control 13 56 Home storage-alteration-eventl 13 57 Home space-switch-event control 13 58 Secondary real-space control 13 60–61 Home designation-type control 13 62–63 Home table length 14 32 Set to 1 14 33 Set to 1 14 34 Extended save-area control (ESA/390-compatibility mode