The Western Design Center (WDC) 65C02 microprocessor is an enhanced CMOS version of the popular nMOS-based 8-bit MOS Technology 6502. It uses less power than the original 6502, fixes several problems, and adds new instructions and addressing modes. The power usage is on the order of 10 to 20 times less than the original 6502 running at the same speed; its reduced power consumption has made it useful in portable computer roles and industrial microcontroller systems. The 65C02 has also been used in some home computers, as well as in embedded applications, including implanted medical devices.
Development of the WDC 65C02 began in 1981 with samples released in early 1983. The 65C02 was officially released sometime shortly after. WDC licensed the design to Synertek, NCR, GTE Microcircuits, and Rockwell Semiconductor. Rockwell's primary interest was in the embedded market and asked for several new commands to be added to aid in this role. These were later copied back into the baseline version, at which point WDC added two new commands of their own to create the W65C02. Sanyo later licensed the design as well, and Seiko Epson produced a further modified version as the HuC6280.
Early versions used 40-pin DIP packaging, and were available in 1, 2 and 4 MHz versions, matching the speeds of the original nMOS versions. Later versions were produced in PLCC and QFP packages, as well as PDIP, and with much higher clock speed ratings. The current version from WDC, the W65C02S-14 has a fully static core and officially runs at speeds up to 14 MHz when powered at 5 volts.
Introduction and features The 65C02 is a low cost, general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. The register set is small, with a single 8-bit accumulator (A), two 8-bit index registers (X and Y), an 8-bit status register (P), and a 16-bit program counter (PC). In addition to the single accumulator, the first 256 bytes of RAM, the "zero page" ($0000 to $00FF), allow faster access through addressing modes that use an 8-bit memory address instead of a 16-bit address. The stack lies in the next 256 bytes, page one ($0100 to $01FF), and cannot be moved or extended. The stack grows downward with the stack pointer (S or SP) starting at $01FF and decrementing with each byte that is pushed. The 65C02 has a variable-length instruction set, varying between one and three bytes per instruction.
The basic architecture of the 65C02 is identical to the original 6502, and may be considered a low-power implementation of that design. At 1 MHz, the most popular speed for the original 6502, the 65C02 requires only 20 mW, while the original uses 450 mW, a reduction of over twenty times. The manually optimized core and low power use is intended to make the 65C02 well suited for low power system-on-chip (SoC) designs.
A Verilog hardware description model is available for designing the W65C02S core into an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). As is common in the semiconductor industry, WDC offers a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.
The W65C02S6T is the production version , and is available in PDIP-40, PLCC-44 and QFP-44 packages. The maximum officially supported Ø2 (primary) clock speed is 14 MHz when operated at 5 volts, indicated by a –14 part number suffix (hobbyists have developed 65C02 homebrew systems that run significantly faster than the official rating). The "S" designation indicates that the part has a fully static core, a feature that supports stopping the Ø2 clock in either phase with no loss of state. Typical microprocessors not implemented in CMOS have dynamic cores and will lose state (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.
The "6T" designation indicates the process geometry (0.6µ) and that Taiwan Semiconductor Manufacturing Company (TSMC) is the foundry that produces WDC's wafers.
+ 65C02 registers 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers A Accumulator Index registers X X Index Register Y Y Index Register 0 0 0 0 0 0 0 1 S Stack Pointer Program counter PC Program Counter Status register N V - B D I Z C Status Register
General logic features 8-bit data bus. 16-bit address bus (providing an address space of 64 KB). 8-bit arithmetic logic unit (ALU). 8-bit processor registers: accumulator. stack pointer. index registers. status register. 16-bit program counter. 69 instructions, implemented by 212 operation codes. 16 addressing modes, including zero page addressing.
Logic features Vector pull (VPB) output indicates when interrupt vectors are being addressed. Memory lock (MLB) output indicates to other bus masters when a read–modify–write instruction is being processed. WAit-for-Interrupt (WAI) and SToP (STP, stop-the-clock) instructions reduce power consumption, decrease interrupt latency and enable synchronization with external events.
Electrical features Supply voltage specified at 1.71 V to 5.25 V. Current consumption (core) of 0.15 and 1.5 mA per MHz at 1.89 V and 5.25 V respectively. Variable length instruction set, enabling code size optimization over fixed length instruction set processors, results in power savings. Fully static core allows stopping the clock to conserve power.
Clocking features The W65C02S may be operated at any convenient supply voltage (VDD) between 1.8 and 5 volts (±5%). The data sheet AC characteristics table lists operational characteristics at 5 V at 14 MHz, 3.3 V or 3 V at 8 MHz, 2.5 V at 4 MHz, and 1.8 V at 2 MHz. This information may be an artifact of an earlier data sheet, as a graph indicates that typical devices are capable of operation at higher speeds than suggested by the AC characteristics table, and that reliable operation at 20 MHz should be readily attainable with VDD at 5 volts, assuming the supporting hardware will allow it.
The W65C02S support for arbitrary clock rates allows it to use a clock that runs at a rate ideal for some other part of the system, such as 13.5 MHz (digital SDTV luma sampling rate), 14.31818 MHz (NTSC color carrier frequency × 4), 14.75 MHz (PAL square pixels), 14.7456 (serial bit rate crystal), etc., as long as VDD is sufficient to support the frequency. Designer Bill Mensch has pointed out that FMAX is affected by off-chip factors, such as the capacitive load on the microprocessor's pins. Minimizing load by using short signal tracks and fewest devices helps raise FMAX. The PLCC and QFP packages have less pin-to-pin capacitance than the PDIP package, and are more economical in the use of printed circuit board space.
WDC has reported that FPGA realizations of the W65C02S have been successfully operated at 200 MHz.
Comparison with the NMOS 6502 Basic architecture Although the 65C02 can mostly be thought of as a low-power 6502, it also fixes several bugs found in the original and adds new instructions, addressing modes and features that can assist the programmer in writing smaller and faster-executing programs. It is estimated that the average 6502 assembly language program can be made 10 to 15 percent smaller on the 65C02 and see a similar improvement in performance, largely through avoided memory accesses through the use of fewer instructions to accomplish a given task.
Undocumented instructions removed The original 6502 has 56 instructions, which, when combined with different addressing modes, produce a total of 151 opcodes of the possible 256 8-bit opcode patterns. The remaining 105 unused opcodes are undefined, with the set of codes with low-order 4-bits with 3, 7, B or F left entirely unused, the code with low-order 2 having only a single opcode.
On the 6502, some of these leftover codes actually perform computation. Due to the way the 6502's instruction decoder works, simply setting certain bits in the opcode causes parts of the instruction processing to take place. Some of these opcodes immediately crash the processor, while others perform useful functions and were even given unofficial assembler mnemonics by some programmers.
The 65C02 adds new opcodes that use some of these previously undocumented instruction slots. For example, $FF is used for the new BBS instruction. Those which remain truly unused are equivalent to NOPs. 6502 programs using those opcodes will not work on the 65C02.
Bug fixes A flaw that is present in all NMOS variants of the 6502 involves the jump instruction when using indirect addressing. In this addressing mode, the target address of the JMP instruction is fetched from memory, the jump vector, rather than being an operand to the JMP instruction. For example, JMP ($1234) would fetch the value in memory locations (least significant byte) and (most significant byte) and load those values into the program counter, which would then cause the processor to continue execution at the address stored in the vector.
The flaw, which some consider a bug, appears when the vector address ends in , which is the boundary of a memory page. In this case, JMP will fetch the most significant byte of the target address from of the original page rather than of the new page. Hence JMP ($12FF) would get the least significant byte of the target address at and the most significant byte of the target address from rather than . The original 6502 documentation does not state that the address will cross pages in this fashion, so one cannot consider it to be a bug per-se. But many 6502 users perceived this complication to be a weakness, so it was eliminated in the 65C02 at the cost of spending another cycle to update the pointer.
Another by-design weakness that was revised by popular demand, the state of the (D)ecimal flag in the NMOS 6502's status register is undefined after a reset or interrupt. This means programmers have to set the flag to a known value in order to avoid random errors caused by arithmetic operations performed in the mode other than the one intended, constituting software bugs. As a result, one finds a CLD instruction (CLear Decimal) in almost all 6502 interrupt handlers, as well as early in the reset code. The 65C02 automatically clears this flag after pushing the status register onto the stack in response any interrupt or in response to a hardware reset, thus placing the processor back into binary arithmetic mode. This usually saves a few bytes in the software and eliminates the possibility of a common programming mistake, at the cost of increasing the size of code that runs in decimal mode as programmers have to remember to SED in places they previously assumed it would still be set.
During decimal mode arithmetic, the NMOS 6502 will put the (N)egative, o(V)erflow and (Z)ero flags into officially undefined states. Programmers found that the CPU updates these three flags to reflect the result of underlying binary arithmetic, that is, the flags reflect a result computed prior to the processor performing decimal correction. In contrast, the 65C02 sets these flags according to the result of decimal arithmetic, at the cost of an extra clock cycle per arithmetic instruction. Some writers assert that the V flag on the 65C02 is still incorrect in decimal mode, but the flag may also be considered to be meaningless because decimal arithmetic is always unsigned.