AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. They are 8-bit RISC single-chip microcontrollers based on a modified Harvard architecture. AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time.
AVR microcontrollers are used numerously as embedded systems. They are especially common in hobbyist and educational embedded applications, popularized by their inclusion in many of the Arduino line of open hardware development boards.
The AVR 8-bit microcontroller architecture was introduced in 1997. By 2003, Atmel had shipped 500 million AVR flash microcontrollers.Atmel press release. "Atmel's AVR Microcontroller Ships 500 Million Units".
History The AVR architecture was conceived by two students at the Norwegian Institute of Technology (NTH),Since 1996, NTH has become part of the Norwegian University of Science and Technology (NTNU) Alf-Egil Bogenalfbogen.com blog and Vegard Wollan.Archived at Ghostarchive and the Wayback Machine:
Atmel says that the name AVR is not an acronym and does not stand for anything in particular. The creators of the AVR give no definitive answer as to what the term "AVR" stands for. However, it is commonly accepted that AVR stands for Alf and Vegard's RISC processor. Note that the use of "AVR" in this article generally refers to the 8-bit RISC line of Atmel AVR microcontrollers.
The original AVR MCU was developed at a local ASIC design company in Trondheim, Norway, called Nordic VLSI at the time, now Nordic Semiconductor, where Bogen and Wollan were working as students. It was known as a μRISC (Micro RISC)An introduction to Atmel and the AVR microcontroller and was available as silicon IP/building block from Nordic VLSI. When the technology was sold to Atmel from Nordic VLSI, the internal architecture was further developed by Bogen and Wollan at Atmel Norway, a subsidiary of Atmel. The designers worked closely with compiler writers at IAR Systems to ensure that the AVR instruction set provided efficient compilation of high-level languages.
Among the first of the AVR line was the AT90S8515, which in a 40-pin DIP package has the same pinout as an 8051 microcontroller, including the external multiplexed address and data bus. The polarity of the RESET line was opposite (8051's having an active-high RESET, while the AVR has an active-low RESET), but other than that the pinout was identical.
The Arduino platform, developed for simple electronics projects, was released in 2005 and featured ATmega8 AVR microcontrollers.
Device overview The AVR is a modified Harvard architecture machine, where program and data are stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions.
Basic families AVRs are generally classified into following (the AT- prefix refers to Atmel):
tinyAVR – the ATtiny series
Flash size Frequency[MHz] Package SRAM EEPROM 0.5–32 KB 1.6–20 6–32-pin package 32–3072 bytes 64–512 bytes
The ATtiny series features small package microcontrollers with a limited peripheral set available. However, the improved tinyAVR 0/1/2-series (released in 2016) include: Peripherals equal to or exceed megaAVR 0-series Event System Improved AVRxt instruction set (improved timing of calls), hardware multiply
megaAVR – the ATmega series
Flash size Frequency[MHz] Package SRAM EEPROM 4–256 KB 1.6–20 28–100-pin package 256–16384 bytes 256–4096 bytes
The ATmega series features microcontrollers that provide an extended instruction set (multiply instructions and instructions for handling larger program memories), an extensive peripheral set, a solid amount of program memory, as well as a wide range of pins available. The megaAVR 0-series (released in 2016) also has functionality such as: Event system New peripherals with enhanced functionality Improved AVRxt instruction set (improved timing of calls)
AVR Dx – The AVR Dx family features multiple microcontroller series, focused on HCI, analog signal conditioning and functional safety.
Flash size Frequency[MHz] Package SRAM EEPROM Release year 16–128 KB 20–24 at 1.8–5.5 V 14–64-pin package 4–16 KB 512 bytes 2020
The parts numbers is formatted as AVRffDxpp, where ff is flash size, x is family, and pp is number of pins. Example: AVR128DA64 – 64-pin DA-series with 128k flash. All devices in the AVR Dx family include: an Async Type D timer that can run faster than the CPU 12-bit ADC 10-bit DAC AVR DA-series (early 2020) – The high memory density makes these MCUs well suited for both wired and wireless communication-stack-intensive functions. integrated sensors for capacitative touch measurement (HCI) updated core independent peripherals (CIPs) and analog peripherals no external high frequency crystal AVR DB-series (mid-late 2020) – inherits many features from the DA-family, while adding its own: 2 or 3 on-chip opamps MultiVoltage IO (MVIO) on PORTC Supports external HF crystal AVR DD-series 16–64 KiB Flash 2–8 KiB SRAM 14–32-pin package internal 24 MHz oscillator 7–23-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC) no amplifiers 1 analog comparator Two USARTs, one SPI, one dual-mode TWI Multi-Voltage Input/Output (MVIO) support on 3 or 4 pins on Port C 4 Configurable Custom Logic (CCL) cells, 6 Event System channels AVR EA-series 8–64 KiB Flash 28–48-pin package internal 20 MHz oscillator 24–32-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC) Programmable Gain Amplifier (PGA) with up to 16x gain 2 analog comparators Three USARTs, one SPI, one dual-mode TWI no Multi-Voltage Input/Output (MVIO) 4 Configurable Custom Logic (CCL) cells, 6 Event System channels
XMEGA
Flash size Frequency[MHz] Package SRAM EEPROM Release year 16–256 KB 32 44–100-pin package 1–32 KB 512–2048 bytes —
the ATxmega series offers a wide variety of peripherals and functionality such as: Extended performance features, such as DMA, "Event System", and cryptography support Extensive peripheral set with ADCs
Application-specific AVR megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN, etc.
FPSLIC (AVR with FPGA) FPGA 5k to 40k gates SRAM for the AVR program code, unlike all other AVRs AVR core can run at up to 50 MHzField Programmable System Level Integrated Circuit. .
32-bit AVRs In 2006, Atmel released microcontrollers based on the 32-bit AVR32 architecture. This was a completely different architecture unrelated to the 8-bit AVR, intended to compete with the ARM-based processors. It had a 32-bit data path, SIMD and DSP instructions, along with other audio- and video-processing features. The instruction set was similar to other RISC cores, but it was not compatible with the original AVR (nor any of the various ARM cores). Since then support for AVR32 has been dropped from Linux as of kernel 4.12; compiler support for the architecture in GCC was never mainlined into the compiler's central source-code repository and was available primarily in a vendor-supported fork. At the time that AVR32 was introduced, Atmel had already been a licensee of the ARM architecture, with both ARM7 and ARM9 microcontrollers having been released prior to and concurrently with the AVR32; later Atmel focused most development effort on 32-bit chips with ARM Cortex-M and Cortex-A cores.
Device architecture
The AVRs have 32 single-byte registers and are classified as 8-bit RISC devices.
Flash, EEPROM, and SRAM are all integrated onto a single chip, removing the need for external memory in most applications. Some devices have a parallel external bus option to allow adding additional data memory or memory-mapped devices. Almost all devices (except the smallest TinyAVR chips) have serial interfaces, which can be used to connect larger serial EEPROMs or flash chips.
Program memory Program instructions are stored in non-volatile flash memory. Although the MCUs are 8-bit, each instruction takes one or two 16-bit words. The size of the program memory is usually indicated in the naming of the device itself (e.g., the ATmega64x line has 64 KB of flash, while the ATmega32x line has 32 KB). There is no provision for off-chip program memory; all code executed by the AVR core must reside in the on-chip flash. However, this limitation does not apply to the AT94 FPSLIC AVR/FPGA chips.
Internal data memory The data address space consists of the register file, I/O registers, and SRAM. Some small models also map the program ROM into the data address space, but larger models do not.
Internal registers In the tinyAVR and megaAVR variants of the AVR architecture, the working registers are mapped in as the first 32 data memory addresses (000016–001F16), followed by 64 I/O registers (002016–005F16). In devices with many peripherals, these registers are followed by 160 “extended I/O” registers, only accessible as memory-mapped I/O (006016–00FF16).
Actual SRAM starts after these register sections, at address 006016 or, in devices with "extended I/O", at 010016.
Even though there are separate addressing schemes and optimized opcodes for accessing the register file and the first 64 I/O registers, all can also be addressed and manipulated as if they were in SRAM.
The very smallest of the tinyAVR variants use a reduced architecture with only 16 registers (r0 through r15 are omitted) which are not addressable as memory locations. I/O memory begins at address 000016, followed by SRAM. In addition, these devices have slight deviations from the standard AVR instruction set. Most notably, the direct load/store instructions (LDS/STS) have been reduced from 2 words (32 bits) to 1 word (16 bits), limiting the total direct addressable memory (the sum of both I/O and SRAM) to 128 bytes. Conversely, the indirect load instruction's (LD) 16-bit address space is expanded to also include non-volatile memory such as Flash and configuration bits; therefore, the Load Program Memory (LPM) instruction is unnecessary and omitted. (For detailed info, see Atmel AVR instruction set.)
In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (000016–0FFF16). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space, which can be used optionally for mapping the internal EEPROM to the data address space (100016–1FFF16). The actual SRAM is located after these ranges, starting at 200016.
General-purpose input/output (GPIO) ports Each GPIO port on a tiny or mega AVR drives up to eight pins and is controlled by three 8-bit registers: DDRx, PORTx and PINx, where x is the port identifier.
DDRx: Data Direction Register, configures the pins as either inputs or outputs. PORTx: Output port register. Sets the output value on pins configured as outputs. Enables or disables the pull-up resistor on pins configured as inputs. PINx: Input register, used to read an input signal. On some devices, this register can be used for pin toggling: writing a logic one to a PINx bit toggles the corresponding bit in PORTx, irrespective of the setting of the DDRx bit.atmel.com