The Intel 8085 ("eighty-eighty-five") is an 8-bit microprocessor produced by Intel and introduced in March 1976. It is binary compatible with the more famous Intel 8080. It is the last 8-bit microprocessor developed by Intel. The "5" in the part number highlighted the fact that the 8085 uses a single +5-volt (V) power supply, compared to the 8080's +5, −5, and +12 V, which makes the 8085 easier to integrate into systems that by this time were mostly +5 V.
The other major change was the addition of four new interrupt pins and a serial port, with separate input and output pins. This was often all that was needed in simple systems and eliminated the need for separate integrated circuits to provide this functionality, as well as simplifying the computer bus as a result. The only changes in the instruction set compared to the 8080 were instructions for reading and writing data using these pins.
The 8085 is supplied in a 40-pin DIP package. Given the new pins, this required multiplexing 8-bits of the address (AD0–AD7) bus with the data bus. This means that specifying a complete 16-bit address requires it to be sent via two 8-bit pathways, and one of those two has to be temporarily latched using separate hardware such as a 74LS373. Intel manufactured several support chips with an address latch built in. These include the 8755, with an address latch, 2 KB of EPROM and 16 I/O pins, and the 8155 with 256 bytes of RAM, 22 I/O pins and a 14-bit programmable timer/counter. The multiplexed address/data bus reduced the number of PCB tracks between the 8085 and such memory and I/O chips.
While the 8085 was an improvement on the 8080, it was eclipsed by the Zilog Z80 in the late 1970s and early 1980s, which took over much of the desktop computer market.
Although not widely used in computers, the 8085 had a long life as a microcontroller. Once designed into such products as the DECtape II controller and the VT102 video terminal in the late 1970s, the 8085 served for new production throughout the lifetime of those products.
Description
The 8085 is a conventional von Neumann design based on the Intel 8080. Unlike the 8080 it does not multiplex state signals onto the data bus, but the 8-bit data bus is instead multiplexed with the lower eight bits of the 16-bit address bus to limit the number of pins to 40. State signals are provided by dedicated bus control signal pins and two dedicated bus state ID pins named S0 and S1. Pin 40 is used for the power supply (+5 V) and pin 20 for ground. Pin 39 is used as the Hold pin.
The Intel 8085 processor was designed using nMOS circuitry, with later "H" versions implemented in Intel's enhanced nMOS process known as HMOS II ("High-performance MOS"), which was originally developed for fast static RAM products.Intel Corporation, "New Products: HMOS MCS-85 Chips Uses 20 to 30 Percent Less Power", Solutions, July/August 1981, Page 22 Unlike the 8080, the 8085 requires only a single 5-volt power supply, similar to its competing processors. The 8085 contains approximately 6,500 transistors.The history of the microcomputer-invention and evolution, S Mazor - Proceedings of the IEEE, 1995
The 8085 incorporates the functions of the 8224 (clock generator) and the 8228 (system controller) on chip, increasing the level of integration. A downside compared to similar contemporary designs (such as the Z80) is the fact that the buses require demultiplexing; however, address latches in the Intel 8155, 8355, and 8755 memory chips allow a direct interface, so an 8085 along with these chips is almost a complete system.
The 8085 has extensions to support new interrupts, with three maskable vectored interrupts (RST 7.5, RST 6.5 and RST 5.5), one non-maskable interrupt (TRAP), and one externally serviced interrupt (INTR). Each of these five interrupts has a separate pin on the processor, a feature which permits simple systems to avoid the cost of a separate interrupt controller. The RST 7.5 interrupt is edge triggered (latched), while RST 5.5 and 6.5 are level-sensitive. All interrupts except TRAP are enabled by the EI instruction and disabled by the DI instruction. In addition, the SIM (Set Interrupt Mask) and RIM (Read Interrupt Mask) instructions, the only instructions of the 8085 that are not from the 8080 design, allow each of the three maskable RST interrupts to be individually masked. All three are masked after a normal CPU reset. SIM and RIM also allow the global interrupt mask state and the three independent RST interrupt mask states to be read, the pending-interrupt states of those same three interrupts to be read, the RST 7.5 trigger-latch flip-flop to be reset (cancelling the pending interrupt without servicing it), and serial data to be sent and received via the SOD and SID pins, respectively, all under program control and independently of each other.
SIM and RIM each execute in four clock cycles (T states), making it possible to sample SID and/or toggle SOD considerably faster than it is possible to toggle or sample a signal via any I/O or memory-mapped port, e.g. one of the ports of an 8155. (In this way, SID can be compared to the SO ["Set Overflow"] pin of the 6502 CPU contemporary to the 8085.)
Like the 8080, the 8085 can accommodate slower memories through externally generated wait states (pin 35, READY), and has provisions for Direct Memory Access (DMA) using HOLD and HLDA signals (pins 39 and 38). An improvement over the 8080 is that the 8085 can itself drive a piezoelectric crystal directly connected to it, and a built-in clock generator generates the internal high-amplitude two-phase clock signals at half the crystal frequency (a 6.14 MHz crystal would yield a 3.07 MHz clock, for instance). The internal clock is available on an output pin, to drive peripheral devices or other CPUs in lock-step synchrony with the CPU from which the signal is output. The 8085 can also be clocked by an external oscillator (making it feasible to use the 8085 in synchronous multi-processor systems using a system-wide common clock for all CPUs, or to synchronize the CPU to an external time reference such as that from a video source or a high-precision time reference).
The 8085 is a binary compatible follow-up on the 8080. It supports the complete instruction set of the 8080, with exactly the same instruction behavior, including all effects on the CPU flags (except for the AND/ANI operation, which sets the AC flag differently). This means that the vast majority of object code (any program image in ROM or RAM) that runs successfully on the 8080 can run directly on the 8085 without translation or modification. (Exceptions include timing-critical code and code that is sensitive to the aforementioned difference in the AC flag setting or differences in undocumented CPU behavior.) 8085 instruction timings differ slightly from the 8080—some 8-bit operations, including INR, DCR, and the heavily used MOV r,r instructions, are one clock cycle faster, but instructions that involve 16-bit operations, including stack PUSH (which decrements the 16-bit SP register) generally one cycle slower. Conditional jumps not taken are three clocks faster on the 8085. As mentioned already, only the SIM and RIM instructions were new to the 8085.Note that the Z80 assigns different instructions—two of the Z80's 6 relative jumps—to the opcodes that the 8085 uses for RIM and SIM, making 8085 programs that use these instructions generally unable to run on the Z80 without modification. Since use of these instructions usually relates to 8085-specific hardware features, the necessary program modification would typically be nontrivial.
Programming model + Intel 8085 registers 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers A Flags Program Status Word B C B D E D H L H (indirect address) Index registers SP Stack Pointer Program counter PC Program Counter Status register S Z - AC - P - CY Flags Interrupt Mask Register SO SE - R7.5 MSE E7.5 E6.5 E5.5 SIM (write) SI I7.5 I6.5 I5.5 IE E7.5 E6.5 E5.5 RIM (read)
The processor has seven 8-bit registers accessible to the programmer, named A, B, C, D, E, H, and L, where A is also known as the accumulator. The other six registers can be used as independent byte-registers or as three 16-bit register pairs, BC, DE, and HL (or B, D, H, as referred to in Intel documents), depending on the particular instruction.
Some instructions use HL as a (limited) 16-bit accumulator. As in the 8080, the contents of the memory address pointed to by HL can be accessed as pseudo register M. It also has a 16-bit program counter and a 16-bit stack pointer to memory (replacing the 8008's internal stack). Instructions such as PUSH PSW, POP PSW affect the Program Status Word (accumulator and flags). The accumulator stores the results of arithmetic and logical operations, and the flags register bits (sign, zero, auxiliary carry, parity, and carry flags) are set or cleared according to the results of these operations. The sign flag is set if the result has a negative sign (i.e. it is set if bit 7 of the accumulator is set). The auxiliary or half carry flag is set if a carryover from bit 3 to bit 4 occurred. The parity flag is set to 1 if the parity (number of 1-bits) of the accumulator is even; if odd, it is cleared. The zero flag is set if the result of the operation was 0. Lastly, the carry flag is set if a carryover from bit 7 of the accumulator (the MSB) occurred.
Commands/instructions As in many other 8-bit processors, all instructions are encoded in a single byte (including register-numbers, but excluding immediate data), for simplicity. Some of them are followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. A NOP "no operation" instruction exists, which does not modify any of the registers or flags. Like larger processors, it has CALL and RET instructions for multi-level procedure calls and returns (which can be conditionally executed, like jumps) and instructions to save and restore any 16-bit register-pair on the machine stack. There are also eight one-byte call instructions (RST) for subroutines located at the fixed addresses 00h, 08h, 10h,...,38h. These are intended to be supplied by external hardware in order to invoke a corresponding interrupt-service routine, but are also often employed as fast system calls. One sophisticated instruction is XTHL, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer.
8-bit instructions