Parallel multidimensional digital signal processing (mD-DSP) is defined as the application of parallel programming and multiprocessing to digital signal processing techniques to process digital signals that have more than a single dimension. The use of mD-DSP is fundamental to many application areas such as digital image and videoKeimel, Christian, Martin Rothbucher, Hao Shen, and Klaus Diepold. "Video is a cube." IEEE Signal Processing Magazine 28, no. 6 (2011): 41–49. processing, medical imaging, geophysical signal analysis, sonar, radar, lidar, array processing, computer vision, computational photography, and augmented and virtual reality. However, as the number of dimensions of a signal increases the computational complexity to operate on the signal increases rapidly. This relationship between the number of dimensions and the amount of complexity, related to both time and space, as studied in the field of algorithm analysis, is analogues to the concept of the curse of dimensionality.Hanka, Rudolf, and Thomas P. Harte. "Curse of dimensionality: classifying large multi-dimensional images with neural networks." In Computer Intensive Methods in Control and Signal Processing, pp. 249–260. Birkhäuser Boston, 1997. This large complexity generally results in an extremely long execution run-time of a given mD-DSP application rendering its usage to become impractical for many applications; especially for real-time applications.Saponara, Sergio, Antonio Plaza, Marco Diani, Matthias F. Carlsohn, and Giovanni Corsini. "Special issue on algorithms and architectures for real-time multi-dimensional image processing." J. Real-Time Image Processing 9, no. 3 (2014): 393–396. This long run-time is the primary motivation of applying parallel algorithmic techniques to mD-DSP problems.
Motivation, problem statement, and basic concepts Due to the end of frequency scalingMims, Christopher. "Why CPUs Aren't Getting Any Faster." MIT Technology Review. October 22, 2012. Accessed December 09, 2016. https://www.technologyreview.com/s/421186/why-cpus-arent-getting-any-faster/."Introduction to Parallel Programming With CUDA | Udacity." Introduction to Parallel Programming With CUDA | Udacity. Accessed December 07, 2016. https://www.youtube.com/watch?v=ET9wxEuqp_Y. of processors, which is largely attributed to the effect of Dennard scalingBohr, M., 2007. A 30 year retrospective on Dennard's MOSFET scaling paper. IEEE Solid-State Circuits Society Newsletter, 12(1), pp. 11–13. around the year 2005, a common trend of processor manufacturers was to continue to exploit Moore's lawMoore, Gordon. "Cramming More Components onto Integrated Circuits," Electronics Magazine Vol. 38, No. 8 (April 19, 1965) by increasing the number of processors on a single chip, which are termed multi-core processors as opposed to uniprocessors.Hennessy, John L., and David A. Patterson. Computer architecture: a quantitative approach. Elsevier, 2011.
mD-DSP algorithms exhibit a large amount of complexity, as described in the previous section, which makes efficient implementation difficult in regard to run-time and power consumption. This article primarily addresses basic parallel concepts used to alleviate run-time of common mD-DSP applications. The concept of parallel computing can be applied to mD-DSP applications to exploit the fact that if a problem can be expressed in a parallel algorithmic form, then parallel programming and multiprocessing can be used in an attempt to increase the computational throughput of the mD-DSP procedure on a given hardware platform. An increase in computational throughput can result in a decreased run-time, i.e. a speedup of a specific mD-DSP algorithm.
In addition to increasing computational throughput, a generally considered equally important goal is to maximally utilize the memory bandwidth of a given computing memory architecture. The combination of the computational throughput and memory bandwidth usage can be achieved through the concept of operational intensity, which is summarized in what is referred to as the roofline model.Williams, S., Waterman, A. and Patterson, D., 2009. Roofline: an insightful visual performance model for multicore architectures. Communications of the ACM, 52(4), pp. 65–76. The concepts of operational intensity and the roofline model in general have recently become popular methods of quantifying the performance of mD-DSP algorithms.Ofenbeck, Georg, et al. "Applying the roofline model." Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on. IEEE, 2014.Bernabé, Gregorio, Javier Cuenca, Luis Pedro García, and Domingo Giménez. "Improving an autotuning engine for 3D Fast Wavelet Transform on manycore systems." The Journal of Supercomputing 70, no. 2 (2014): 830–844.
Increasing throughput can be beneficial to strong scaling"Introduction to Parallel Programming With CUDA | Udacity." Introduction to Parallel Programming With CUDA | Udacity. Accessed December 07, 2016. https://www.youtube.com/watch?v=539pseJ3EUc.Humphries, Benjamin, Hansen Zhang, Jiayi Sheng, Raphael Landaverde, and Martin C. Herbordt. "3D FFTs on a Single FPGA." In Field-Programmable Custom Computing Machines (FCCM), 2014 IEEE 22nd Annual International Symposium on, pp. 68–71. IEEE, 2014. of a given mD-DSP algorithm. Another possible benefit of increasing operational intensity is to allow for an increase in weak scaling, which allows the mD-DSP procedure to operate on increased data sizes or larger data sets, which is important for application areas such as data mining and the training of deep neural networksCatanzaro, Bryan. "Scaling Deep Learning." 2015. Accessed December 10, 2016. http://www.highperformancegraphics.org/wp-content/uploads/2016/CatanzaroHPG2016.pdf. using big data.
The goal of parallizing an algorithm is not always to decrease the traditional concept of complexity of the algorithm because the term complexity as used in this context typically refers to the RAM abstract computer model, which by definition is serial. Parallel abstract computer models such as PRAM have been proposed to describe complexity for parallel algorithms such as mD signal processing algorithms.Saybasili, A. Beliz, Alexandros Tzannes, Bernard R. Brooks, and Uzi Vishkin. "Highly Parallel Multi-Dimensional Fast Fourier Transform on Fine-and Coarse-Grained Many-Core Approaches." In Proceedings of the 21st IASTED International Conference, vol. 668, no. 018, p. 107. 2009.
Another factor that is important to the performance of mD-DSP algorithm implementations is the resulting energy consumption and power dissipation.Ukidave, Y., Ziabari, A.K., Mistry, P., Schirner, G. and Kaeli, D., 2013, April. Quantifying the energy efficiency of FFT on heterogeneous platforms. In Performance Analysis of Systems and Software (ISPASS), 2013 IEEE International Symposium on (pp. 235–244). IEEE.
Existing approaches
Parallel implementations of multidimensional discrete fourier transforms As a simple example of an mD-DSP algorithm that is commonly decomposed into a parallel form, let’s consider the parallelization of the discrete Fourier transform, which is generally implemented using a form of the Fast Fourier Transform (FFT). There are hundreds of available software libraries that offer optimized FFT algorithms,"2DECOMP&FFT – Review on Fast Fourier Transform Software." 2DECOMP&FFT – Review on Fast Fourier Transform Software. Accessed December 07, 2016. http://www.2decomp.org/fft.html. and many of which offer parallelized versions of mD-FFT algorithmsSIAM Journal on Scientific Computing 2012, Vol. 34, No. 4, pp. C192–C209.Sandia National Laboratories: Exceptional Service in the National Interest. Accessed December 07, 2016. http://www.sandia.gov/~sjplimp/docs/fft/README.html."FFTE: A Fast Fourier Transform Package." FFTE: A Fast Fourier Transform Package. Accessed December 07, 2016. http://www.ffte.jp/. with the most popular being the parallel versions of the FFTwParallel FFTw. Accessed December 07, 2016. http://www.fftw.org/parallel/parallel-fftw.html. library.
The most straightforward method of paralyzing the DFT is to utilize the row-column decomposition method. The following derivation is a close paraphrasing from the classical text Multidimensional Digital Signal Processing.Dudgeon, Dan E., and Russell M. Mersereau. Multidimensional Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1984. The row-column decomposition can be applied to an arbitrary number of dimensions, but for illustrative purposes, the 2D row-column decomposition of the DFT will be described first. The 2D DFT is defined as
where term is commonly referred to as the twiddle factor of the DFT in the signal processing literature.
The DFT equation can be re-written in the following form
where the quantity inside the brackets is a 2D sequence which we will denote as . We can then express the above equation as the pair of relations
Each column of is the 1D DFT of the corresponding column of . Each row of is the 1D DFT of the corresponding row of . Expressing the 2D-DFT in the above form allows us to see that we can compute a 2D DFT by decomposing it into row and column DFTs. The DFT of each column of can first be computed where the results of which are placed into an intermediate array. Then we can compute the DFT of each row of the intermediate array.
This row-column decomposition process can easily be extended to compute an mD DFT. First, the 1D DFT is computed with respect to one of the independent variables, say , for each value of the remaining variables. Next, 1D DFTs are computed with respect to the variable for all values of the -tuple . We continue in this fashion until all 1D DFTs have been evaluated with respect to all the spatial variables.
The row-column decomposition of the DFT is parallelized in its most simplistic manner by noting that the row and column computations are independent of each other and therefore can be performed on separate processors in parallel. The parallel 1D DFT computations on each processor can then utilize the FFT algorithm for further optimization. One large advantage of this specific method of parallelizing an mD DFT is that each of the 1D FFTs being performed in parallel on separate processors can then be performed in a concurrent fashion on Shared memory multithreaded SIMD processorsPatterson, David A., and John L. Hennessy. Computer organization and design: the hardware/software interface. Newnes, 2013. .
A specifically convenient hardware platform that has the ability to simultaneous perform both parallel and concurrent DFT implementation techniques that is highly amenable to are GPUs due to common GPUs having both a separate set of multithreaded SIMD processors (which are referred to as "streaming multiprocessors" in the CUDA programming language, and "compute units" in the OpenCL language) and individual SIMD lanes (commonly referred to loosely as a "core", or more specifically a CUDA "thread processor" or as an OpenCL "processing element") within each multithreaded SIMD processor.
A disadvantage to this technique of applying a separate FFT on each shared memory multiprocessor is the required interleaving of the data among the shared memory. One of the most popular libraries that utilizes this basic form of concurrent FFT computation is in the shared memory version of the FFTw library."Parallel Versions of FFTW." Parallel FFTW. Accessed December 07, 2016. http://www.fftw.org/parallel/parallel-fftw.html.
Parallel implementations of multidimensional FIR filter structures