Zen is the first iteration in the Zen family of computer processor microarchitectures from AMD. It was first used with their Ryzen series of CPUs in February 2017. The first Zen-based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. The first Zen-based CPUs, codenamed "Summit Ridge", reached the market in early March 2017, Zen-derived Epyc server processors launched in June 2017 and Zen-based APUs arrived in November 2017.
Zen is a clean sheet design that differs from AMD's previous long-standing Bulldozer architecture. Zen-based processors use a 14 nm FinFET process, are reportedly more energy efficient, and can execute significantly more instructions per cycle. SMT has been introduced, allowing each core to run two threads. The cache system has also been redesigned, making the L1 cache write-back. Zen processors use three different sockets: desktop Ryzen chips use the AM4 socket, bringing DDR4 support; the high-end desktop Zen-based Threadripper chips support quad-channel DDR4 memory and offer 64 PCIe 3.0 lanes (vs 24 lanes), using the TR4 socket; and Epyc server processors offer 128 PCIe 3.0 lanes and octa-channel DDR4 using the SP3 socket.
Zen is based on a SoC design. The memory controller and the PCIe, SATA, and USB controllers are incorporated into the same chip(s) as the processor cores. This has advantages in bandwidth and power, at the expense of chip complexity and die area. This SoC design allows the Zen microarchitecture to scale from laptops and small-form factor mini PCs to high-end desktops and servers.
By 2020, 260 million Zen cores have already been shipped by AMD.AMD Shipped 260 Million Zen Cores by 2020 . AnandTech.
Design
According to AMD, the main focus of Zen is on increasing per-core performance.
New or improved features include:Software Optimization Guide for AMD Family 17h Processors / AMD, June 2017
The L1 cache has been changed from write-through to write-back, allowing for lower latency and higher bandwidth. SMT (simultaneous multithreading) architecture allows for two threads per core, a departure from the CMT (clustered multi-thread) design used in the previous Bulldozer architecture. This is a feature previously offered in some IBM, Intel and Oracle processors. A fundamental building block for all Zen-based CPUs is the Core Complex (CCX) consisting of four cores and their associated caches. Processors with more than four cores consist of multiple CCXs connected by Infinity Fabric. Processors with non-multiple-of-four core counts have some cores disabled. Four ALUs, two AGUs/load–store units, and two floating-point units per core. Newly introduced "large" micro-operation cache. Each SMT core can dispatch up to six micro-ops per cycle (a combination of 6 integer micro-ops and 4 floating point micro-ops per cycle). Close to 2× faster L1 and L2 bandwidth, with total L3 cache bandwidth up 5×. Clock gating. Larger retire, load, and store queues. Improved branch prediction using a hashed perceptron system with Indirect Target Array similar to the Bobcat microarchitecture, something that has been compared to a neural network by AMD engineer Mike Clark. The branch predictor is decoupled from the fetch stage. A dedicated stack engine for modifying the stack pointer, similar to that of Intel Haswell and Broadwell processors. Move elimination, a method that reduces physical data movement to reduce power consumption. Binary compatibility with Intel's Skylake (excluding VT-x and private MSRs): RDSEED support, a set of high-performance hardware random number generator instructions introduced in Broadwell. Support for the SMAP, SMEP, XSAVEC/XSAVES/XRSTORS, and CLFLUSHOPT instructions. ADX support. SHA support. CLZERO instruction for clearing a cache line. Useful for handling ECC-related Machine-check exceptions. PTE (page table entry) coalescing, which combines 4kB page tables into 32kB page size. "Pure Power" (more accurate power monitoring sensors). Support for intel-style running average power limit (RAPL) measurement. Smart Prefetch. Precision Boost. eXtended Frequency Range (XFR), an automated overclocking feature which boosts clock speeds beyond the advertised turbo frequency.
The Zen architecture is built on a 14 nm FinFET process subcontracted to GlobalFoundries, which in turn licenses its 14nm process from Samsung Electronics. This gives greater efficiency than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs, respectively. The "Summit Ridge" Zen family of CPUs use the AM4 socket and feature DDR4 support and a 95 W TDP (thermal design power). While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance-oriented mobile products with up to four Zen cores.
Each Zen core can decode four instructions per clock cycle and includes a micro-op cache which feeds two schedulers, one each for the integer and floating point segments. Each core has two address generation units, four integer units, and four floating point units. Two of the floating point units are adders, and two are multiply-adders. However, using multiply-add-operations may prevent simultaneous add operation in one of the adder units.AMD, "Software Optimization Guider for AMD Family 17h Processors" There are also improvements in the branch predictor. The L1 cache size is 64 KB for instructions per core and 32 KB for data per core. The L2 cache size 512 KB per core, and the L3 is 1–2 MB per core. L3 caches offer 5× the bandwidth of previous AMD designs.
History and development AMD began planning the Zen microarchitecture shortly after re-hiring Jim Keller in August 2012. AMD formally revealed Zen in 2015.
The team in charge of Zen was led by Keller (who left in September 2015 after a 3-year tenure) and Zen Team Leader Suzanne Plummer. The Chief Architect of Zen was AMD Senior Fellow Michael Clark.
Zen was originally planned for 2017 following the ARM64-based K12 sister core, but on AMD's 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design, to allow it to enter the market within the 2016 timeframe, with the release of the first Zen-based processors expected for October 2016.
In November 2015, a source inside AMD reported that Zen microprocessors had been tested and "met all expectations" with "no significant bottlenecks found".
In December 2015, it was rumored that Samsung may have been contracted as a fabricator for AMD's 14 nm FinFET processors, including both Zen and AMD's then-upcoming Polaris GPU architecture.. This was clarified by AMD's July 2016 announcement that products had been successfully produced on Samsung's 14 nm FinFET process. AMD stated Samsung would be used "if needed", arguing this would reduce risk for AMD by decreasing dependence on any one foundry.
In December 2019, AMD started putting out first generation Ryzen products built using the second generation Zen+ architecture.
Advantages over predecessors
Manufacturing process Processors based on Zen use 14 nm FinFET silicon. These processors are reportedly produced at GlobalFoundries. Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their Steamroller and Excavator microarchitectures. The immediate competition, Intel's Skylake and Kaby Lake microarchitecture, are also fabricated on 14 nm FinFET; though Intel planned to begin the release of 10 nm parts later in 2017. Intel was unable to reach this goal, and in 2021, only mobile chips have been produced with the 10nm process. In comparison to Intel's 14 nm FinFET, AMD claimed in February 2017 the Zen cores would be 10% smaller. Intel has later announced in July 2018 that 10nm mainstream processors should not be expected before the second half of 2019.
For identical designs, these die shrinks would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125W, or ~45W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.
Performance One of Zen's major goals in 2016 was to focus on performance per-core, and it was targeting a 40% improvement in instructions per cycle (IPC) over its predecessor. Excavator, in comparison, offered 4–15% improvement over previous architectures. AMD announced the final Zen microarchitecture actually achieved 52% improvement in IPC over Excavator. The inclusion of SMT also allows each core to process up to two threads, increasing processing throughput by better use of available resources.
The Zen processors also employ sensors across the chip to dynamically scale frequency and voltage. This allows for the maximum frequency to be dynamically and automatically defined by the processor itself based upon available cooling.
AMD has demonstrated an 8-core/16-thread Zen processor outperforming an equally-clocked Intel Broadwell-E processor in Blender rendering and HandBrake benchmarks.
Zen supports AVX2 but it requires two clock cycles to complete each AVX2 instruction compared to Intel's one. This difference was corrected in Zen 2.
Memory Zen supports DDR4 memory (up to eight channels) and ECC.
Pre-release reports stated APUs using the Zen architecture would also support High Bandwidth Memory (HBM). However, the first demonstrated APU did not use HBM. Previous APUs from AMD relied on shared memory for both the GPU and the CPU.
Power consumption and heat output Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non-FinFET predecessors (for equivalent designs), or be more computationally powerful at equivalent heat output/power consumption.
Zen also uses clock gating, reducing the frequency of underutilized portions of the core to save power. This comes from AMD's SenseMI technology, using sensors across the chip to dynamically scale frequency and voltage.
Enhanced security and virtualization support Zen added support for AMD's Secure Memory Encryption (SME) also known as Transparent Secure Memory Encryption (TSME), and AMD's Secure Encrypted Virtualization (SEV). Secure Memory Encryption is real-time memory encryption done per page table entry. Encryption and verification occur on an AES with GCM hardware engine (which integrated into the memory controller), and keys are managed by the onchip "Security" Processor (ARM Cortex-A5) at boot time to encrypt each page, allowing any memory (including non-volatile varieties) to be encrypted. AMD SME also makes the contents of the memory more resistant to memory snooping and cold boot attacks.
The Secure Encrypted Virtualization (SEV) feature allows the memory contents of a virtual machine (VM) to be transparently encrypted with a key unique to the guest VM. The memory controller contains a high-performance encryption engine which can be programmed with multiple keys for use by different VMs in the system. The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes an API for these tasks.
On client processors, SME and SEV are offered on AMD's Ryzen Pro series.
Connectivity Incorporating much of the southbridge into the SoC, the Zen CPU includes SATA, USB, and PCI Express NVMe links. This can be augmented by available Socket AM4 chipsets which add connectivity options including additional SATA and USB connections, and support for AMD's Crossfire and Nvidia's SLI.