This is a comparison of ARM instruction set architecture application processor cores designed by Arm Holdings (ARM Cortex-A) and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.

ARMv7-A This is a table comparing 32-bit central processing units that implement the ARMv7-A (A means Application) instruction set architecture and mandatory or optional extensions of it, the last AArch32.

CoreOut-of-order executionFPUFPUregistersNEON(SIMD)big.LITTLEroleProcesstechnologyL0cacheL1cacheL2cacheARM Cortex-A5 8 40/28 nm 4–64 KiB / core 1, 2, 41.570xC05ARM Cortex-A75840/28 nm 8–64 KiB / coreup to 1 MiB (optional)1, 2, 4, 81.90xC07ARM Cortex-A821365/55/45 nm 32 KiB + 32 KiB256 or 512 (typical) KiB12.00xC08ARM Cortex-A938–1165/45/40/32/28 nm 32 KiB + 32 KiB1 MiB1, 2, 42.50xC09ARM Cortex-A12 1128 nm 32–64 KiB + 32 KiB256 KiB, to 8 MiB1, 2, 43.00xC0DARM Cortex-A15815/17-2532/28/20 nm 32 KiB + 32 KiB per coreup to 4 MiB per cluster, up to 8 MiB per chip2, 4, 8 (4×2)3.5 to 4.010xC0FARM Cortex-A17 11+28 nm 32 KiB + 32 KiB per core256 KiB, up to 8 MiBup to 44.00xC0EQualcomm Scorpion310 65/45 nm 32 KiB + 32 KiB256 KiB (single-core)512 KiB (dual-core)1, 22.10x00FQualcomm Krait711 28 nm4 KiB + 4 KiB direct mapped16 KiB + 16 KiB 4-way set associative1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core)2, 43.3 (Krait 200)3.39 (Krait 300)3.39 (Krait 400)3.51 (Krait 450)0x04D0x06FSwift51232 nm 32 KiB + 32 KiB1 MiB23.5?CoreOut-of-order executionFPUFPUregistersNEON(SIMD)big.LITTLEroleProcesstechnologyL0cacheL1cacheL2cache

ARMv8-A

This is a table of central processing units (CPUs) that implement the ARMv8-A instruction set architecture and mandatory or optional extensions of it. Almost all of these CPUs support the 64-bit AArch64 Execution State, and many of them support the 32-bit AArch32 Execution State for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7-A and NEON (SIMD) CPUs. Some of these CPUs have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the CPUs are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

Company Core rowspan="2" Revision 32-bit support Decode Pipelinedepth Out-of-orderexecution Branchprediction big.LITTLE role rowspan="2" SIMD Fab (in nm) rowspan="2" L0 cache L1 cacheInstr + Data(in KiB) L2 cache L3 cache rowspan="2" rowspan="2" Clock rate rowspan="2" Have itEntries ARM Cortex-A32 2017 ARMv8.0-A(only 32-bit) 2-wide 8 0 28 8–64 + 8–64 0–1 MiB 1–4+ 2.3 0xD01Cortex-A34 2019ARMv8.0-A 2-wide 8 0 8–64 + 8–64 0–1 MiB 1–4+ 0xD02 Cortex-A35 2017 ARMv8.0-A 2-wide 8 0 28 / 16 /14 / 10 8–64 + 8–64 0 / 128 KiB–1 MiB 1–4+ 1.7-1.85 0xD04 Cortex-A53 2014 ARMv8.0-A 2-wide 8 0 Conditional+Indirect branchprediction 2 28 / 20 /16 / 14 / 12 / 10 / 4 8–64 + 8–64 128 KiB–2 MiB 1–4+ 2.24 0xD03 Cortex-A55 2017 ARMv8.2-A 2-wide 8 0 2 28 / 20 /16 / 14 / 12 / 10 / 5 16–64 + 16–64 0–256 KiB/core 1–8+ 2.65Based on 18% perf. increment over Cortex-A53 0xD05 Cortex-A57 2013 ARMv8.0-A 3-wide 15 3-wide dispatch 8 28 / 20 /16 / 14 48 + 32 0.5–2 MiB 1–4+ 4.1-4.8 0xD07 Cortex-A652019 ARMv8.2-A 2-wide 10-12 4-wide dispatch 9 SMT2 32–64 + 32–64 KiB 0, 64–256 KiB 0, 0.5–4 MiB 1-8 0xD06 Cortex-A65AE2019 ARMv8.2-A 2 SMT2 32–64 + 32–64 KiB 64–256 KiB 0, 0.5–4 MiB 1–8 0xD43 Cortex-A72 2015 ARMv8.0-A 3-wide 15 5-wide dispatch 8 28 / 16 48 + 32 0.5–4 MiB No 1–4+ 4.7-6.3 0xD08 Cortex-A73 2016 ARMv8.0-A 2-wide 11–12 4-wide dispatch 7 28 / 16 / 10 64 + 32/64 1–8 MiB No 1–4+ 4.8–8.5 0xD09Cortex-A752017ARMv8.2-A 3-wide11–13 6-wide dispatch8? 2*128b28 / 16 / 10 64 + 64256–512 KiB/core0–4 MiB1–8+ 6.1–9.50xD0ACortex-A762018ARMv8.2-A4-wide11–13 8-wide dispatch 128 8 2*128b10 / 7 64 + 64256–512 KiB/core1–4 MiB1–4 6.40xD0BCortex-A76AE2018ARMv8.2-A 128 0xD0ECortex-A772019ARMv8.2-A4-wide11–13 10-wide dispatch160 122*128b7 1.5K entries64 + 64256–512 KiB/core1–4 MiB1–47.3According to ARM, the Cortex-A77 has a 20% IPC single-thread performance improvement over its predecessor in Geekbench 4, 23% in SPECint2006, 35% in SPECfp2006, 20% in SPECint2017, and 25% in SPECfp20170xD0DCortex-A782020ARMv8.2-A4-wide160Yes132*128b 1.5K entries32/64 + 32/64256–512 KiB/core1–4 MiB1–47.6-8.20xD41Cortex-X12020ARMv8.2-A5-wide224Yes154*128b 3K entries64 + 64up to 1 MiBup to 8 MiBcustom10-110xD44AppleCyclone 2013 ARMv8.0-A 6-wide 16 192 9 28 64 + 64 1 MiB 4 MiB 2 1.3–1.4 GHz Typhoon 2014 ARMv8.0‑A 6-wide 16 9 20 64 + 64 1 MiB 4 MiB 2, 3 (A8X) 1.1–1.5 GHz Twister 2015 ARMv8.0‑A 6-wide 16 9 16 / 14 64 + 64 3 MiB 4 MiBNo (A9X) 2 1.85–2.26 GHzHurricane2016ARMv8.0‑A6-wide1693*128b16 (A10)10 (A10X) 64 + 643 MiB (A10)8 MiB (A10X)4 MiB (A10)No (A10X)2x Hurricane (A10) 3x Hurricane (A10X)2.34–2.36 GHzZephyrARMv8.0‑A3-wide12 516 (A10)10 (A10X) 32 + 321 MiB4 MiB (A10)No (A10X)2x Zephyr (A10) 3x Zephyr (A10X)1.09–1.3 GHzMonsoon2017ARMv8.2‑A7-wide16113*128b10 64 + 648 MiB 2x Monsoon2.39 GHzMistralARMv8.2‑A3-wide12 510 32 + 321 MiB 4× Mistral1.19 GHzVortex2018ARMv8.3‑A7-wide16113*128b7 128 + 1288 MiB 2x Vortex (A12) 4x Vortex (A12X/A12Z)2.49 GHzTempestARMv8.3‑A3-wide12 57 32 + 322 MiB 4x Tempest1.59 GHzLightning2019ARMv8.4‑A8-wide16560113*128b7 128 + 1288 MiB 2x Lightning2.65 GHzThunderARMv8.4‑A3-wide12 57 96 + 484 MiB 4x Thunder1.8 GHzFirestorm2020ARMv8.4-A8-wide630144*128b5 192 + 1288 MiB (A14)12 MiB (M1)24 MiB (M1 Pro/M1 Max)48 MiB (M1 Ultra) 2x Firestorm (A14) 4x Firestorm (M1) 6x or 8x Firestorm (M1 Pro) 8x Firestorm (M1 Max) 16x Firestorm (M1 Ultra)3.0–3.23 GHzIcestormARMv8.4-A4-wide110 72*128b5 128 + 644 MiB8 MiB (M1 Ultra) 4x Icestorm (A14/M1) 2x Icestorm (M1 Pro/Max) 4x Icestorm (M1 Ultra)1.82–2.06 GHzAvalanche2021ARMv8.6‑A8-wide144*128b5 192 + 12812 MiB (A15)16 MiB (M2)32 MiB (M2 Pro/M2 Max)64 MiB (M2 Ultra) 2x Avalanche (A15) 4x Avalanche (M2) 6x or 8x Avalanche (M2 Pro) 8x Avalanche (M2 Max) 16x Avalanche (M2 Ultra)2.93–3.49 GHzBlizzardARMv8.6‑A4-wide 82*128b5 128 + 644 MiB8 MiB (M2 Ultra) 4x Blizzard2.02–2.42 GHzEverest2022ARMv8.6‑A8-wide144*128b5 192 + 12816 MiB 2x Everest3.46 GHzSawtoothARMv8.6‑A4-wide 82*128b5 128 + 644 MiB 4x Sawtooth2.02 GHzNvidiaDenver2014ARMv8‑A 2-wide ARM or binary translated VLIW 13 If translated into VLIW code by software Direct+Indirect branchprediction 7 28 128 + 64 2 MiB 2 Denver 22016 ARMv8‑A 13 If translated into VLIW code by software Direct+Indirect branchprediction "Super" Nvidia's own implementation 16 128 + 64 2 MiB 2 Carmel2018 ARMv8.2‑A Direct+Indirect branchprediction 12 128 + 64 2 MiB (4 MiB @ 8 cores) 2 (+ 8) 6.5-7.4 CaviumThunderX 2014 ARMv8-A 2-wide 9 28 78 + 32 16 MiB No 8–16, 24–48 ThunderX2 2018 ARMv8.1-A 4-wide"4 μops" 16SMT4 32 + 32(data 8-way) 256 KiBper core 1 MiBper core 16–32 Marvell ThunderX3 2020 ARMv8.3+ 8-wide 4-wide dispatch 7 7SMT4 64 + 32 512 KiBper core 90 MiB 60 Applied MicroHelix 2014 40 / 28 No 32 + 32 (per core;write-throughw/parity) 256 KiB sharedper core pair (with ECC) 1 MiB/core 2, 4, 8 X-Gene 2013 4-wide 15 40 No 8 MiB 8 4.2 X-Gene 2 2015 4-wide 15 28 No 8 MiB 8 4.2 X-Gene 3 2017 16 No 32 MiB 32 QualcommKryo 2015 ARMv8-A 14 No 32+24 0.5–1 MiB 2+2 6.3 Kryo 200 2016ARMv8-A2-wide11–12 7-wide dispatch 714 / 11 / 10 / 6 rowspan="2" rowspan="2" 64 + 32/64?512 KiB/Gold Core rowspan="2" 41.8–2.45 GHz2-wide8 0 Conditional+Indirect branchprediction28–64? + 8–64?256 KiB/Silver Core41.8–1.9 GHzKryo 3002017ARMv8.2-A3-wide11–13 8-wide dispatch 810 rowspan="2" rowspan="2" 64+64256 KiB/Gold Core2 MiB2, 42.0–2.95 GHz2-wide8 0 Conditional+Indirect branchprediction 2816–64? + 16–64?128 KiB/Silver4, 61.7–1.8 GHzKryo 4002018ARMv8.2-A4-wide11–13 8-wide dispatch 811 / 8 / 7 rowspan="2" rowspan="2" 64 + 64512 KiB/Gold Prime 256 KiB/Gold2 MiB2, 1+1, 4, 1+3 2.0–2.96 GHz2-wide8 0 Conditional+Indirect branchprediction 216–64? + 16–64?128 KiB/Silver4, 61.7–1.8 GHzKryo 5002019ARMv8.2-A4-wide11–13 8-wide dispatch 8 / 7 rowspan="2" 512 KiB/Gold Prime 256 KiB/Gold3 MiB2, 1+32.0–3.2 GHz2-wide8 0 Conditional+Indirect branchprediction2 128 KiB/Silver4, 61.7–1.8 GHzKryo 6002020ARMv8.4-A4-wide11–13 8-wide dispatch 6 / 5 rowspan="2" 64 + 641024 KiB/Gold Prime 512 KiB/Gold4 MiB2, 1+32.2–3.0 GHz2-wide8 0 Conditional+Indirect branchprediction2 128 KiB/Silver4, 61.7–1.8 GHz Falkor 2017 "ARMv8.1-A features" 4-wide 10–15 8 10 24 KiB 88 + 32 500KiB 1.25MiB 40–48 Samsung M1 2016 ARMv8-A 4-wide 13 9-wide dispatch 96 8 14 No 64 + 32 2 MiB No 4 2.6 GHzM22017ARMv8-A4-wide100 10 64 + 642 MiB 42.3 GHz M3 2018 ARMv8.2-A 6-wide 15 12-wide dispatch 228 12 10 No 64 + 64 512 KiB per core 4096KB 4 2.7 GHz M42019ARMv8.2-A6-wide15 12-wide dispatch 228 128 / 7 64 + 64512 KiB per core3072KB22.73 GHzM52020ARMv8.2-A6-wide 12-wide dispatch 228 7 64 + 64512 KiB per core3072KB22.73 GHz Fujitsu A64FX2019ARMv8.2-A4/2-wide7+ 5-way? 8+2*512b7 64 + 648MiB per 12+1 cores 48+41.9 GHz+ HiSilicon TaiShan V1102019ARMv8.2-A4-wide 87 64 + 64512 KiB per core1 MiB per core Company Core Revision 32-bit support Decode PipelinedepthOut-of-orderexecutionBranchpredictionbig.LITTLE role Exec. portsSIMD Fab (in nm)L0 cacheL1 cacheInstr + Data(in KiB) L2 cache L3 cache Clock rate

ARMv9-A

+CompanyCore rowspan="2" Revision32-bit supportDecode rowspan="2" Out-of-order executionBranchprediction rowspan="2" rowspan="2" rowspan="2" rowspan="2" rowspan="2" L0 cacheL1 cacheInstr + Data(in KiB)L2 cacheL3 cache rowspan="2" rowspan="2" Clock rate rowspan="2" Have itEntriesARMCortex-A510May 2021ARMv9-A3-wide8 stages (does not support out-of-order execution)Advanced techniques similar to larger cores, specifics not disclosedLITTLE2 execution ports5nm32 or 64 KB eachConfigurable, typically 128 KB to 512 KBTypically paired with Cortex-A710 in configurations (e.g., 1+3)Not explicitly stated, but performance uplift of 35% over A55Up to 2.85 GHz (varies by implementation)0xD46Cortex-A710May 2021ARMv9-A4-wide10 stages160 entriesEnhanced with larger structures and better accuracybig13 execution ports5nmNot specified64/128 KiB each256/512 KiBOptional, up to 16 MiBTypically 1+3+4 (big.LITTLE)Not specified in resultsUp to 3.0 GHz (approx.)0xD47Cortex-A715June 2022ARMv9-A5-wide10 stages160 entriesAdvanced branch prediction capabilitiesbig13 execution ports4nmNot specified64 KiB each1 MiB16 MiB (in certain configurations)1+3+4 or similar setupsNot specified, but designed for high efficiencyUp to 2.8 GHz0xD4DCortex-X2May 2021ARMv9-A5-wide10 stages288 entriesAdvanced, with improved accuracybig15 execution ports5nmNot specified64 KiB each1 MiB8 MiB1+3+4 (X2+A710+A510)Not specifiedUp to 3.2 GHz0xD48Cortex-X3June 2022ARMv9-A6-wide9 stages320 entriesAdvanced branch prediction capabilitiesbig15 execution ports4nmNot specified64 KiB each1 MiB16 MiB1+3+4 or up to 8+4Not specifiedUp to 3.6 GHz0xD4E

See also AArch64 List of ARM processors List of products using ARM processors Microarchitecture

Notes

References