A physically unclonable function (PUF) is a physical entity that can serve as a hardware security primitive, particularly useful in authentication and anti-counterfeiting applications. PUFs generate identifiers based on unique, complex physical structures or responses that are difficult to replicate or model. Their evaluation typically involves measuring physical properties or optical features associated with the specific device.

PUFs leverage inherently non-reproducible physical properties to generate unique identifiers, making them promising for authentication and anti-counterfeiting applications. All PUFs are subject to environmental variations such as temperature, supply voltage, or electromagnetic interference, which can affect their responses. Their utility lies not only in producing random outputs, but in reliably reproducing the same response under varying conditions for a given challenge. Compared to traditional anti-counterfeit methods like holograms, PUFs are harder to clone due to the intrinsic randomness of their fabrication.

PUF categorization

Measurement process

One way to categorise the numerous PUF concepts is by how the source of variation within each PUF is measured. For instance some PUFs examine how the source of uniqueness interacts with, or influences, an electronic signal to derive the signature measurement while others examine the effects on the reflection of incident light, or another optical process. This also typically correlates with the intended application for each PUF concept. As an example, PUFs that probe uniqueness through electronic characterization are most suitable for authenticating electronic circuits or components due to the ease of integration. On the other hand, PUFs that authenticate physical objects tend to probe the PUF using a second process, such as optical or radio frequency methods, that are then converted into electronic signal forming a hybrid measurement system. This allows for easier communication at a distance between the separate physical authenticating tag or object and the evaluating device.

Randomness source

One major way that PUFs are categorized is based on examining from where the randomness or variation of the device is derived. This source of uniqueness is either applied in an explicit manner, through the deliberate addition of extra manufacturing steps, or occurring in an implicit manner, as part of the typical manufacture processes. For example, in the case of electronic PUFs manufactured in CMOS, adding additional CMOS components is possible without introducing extra fabrication steps, and would count as an implicit source of randomness, as would deriving randomness from components that were already part of the design to start with. Adding, for example, a randomized dielectric coating for the sole purpose of PUF fingerprinting would add additional manufacturing steps and would make the PUF concept or implementation fall into the explicit category. Implicit randomness sources show benefit in that they do not have additional costs associated with introducing more manufacturing steps, and that randomness derived from the inherent variation of the device's typical manufacture process cannot be as directly manipulated. Explicit randomness sources can show benefit in that the source of randomness can be deliberately chosen, for instance to maximize variation (and therefore entropy yield) or increase cloning difficulty (for example harnessing randomness from smaller feature sizes).

Intrinsic evaluation

In a similar manner to the classification of a PUF by its randomness source, PUF concepts can be divided by whether or not they can evaluate in an intrinsic manner. A PUF is described as intrinsic if its randomness is of implicit origin and can evaluate itself internally. This means that the mechanism for characterizing the PUF is intrinsic to, or embedded within, the evaluating device itself. This property can currently only be held by PUFs of entirely electronic design, as the evaluation processing can only be done through the involvement of electronic circuitry, and therefore can only be inseparable to an electronic randomness probing mechanism. Intrinsic evaluation is beneficial as it can allow this evaluation processing and post-processing (such as error correction or hashing) to occur without having the unprocessed PUF readout exposed externally. This incorporation of the randomness characterization and evaluation processing into one unit reduces the risk of man-in-the-middle and side-channel attacks aimed at the communication between the two areas.

A categorized sample of the collection of over 40 PUF concepts so far suggested PUF name Measurement process Randomness source Intrinsic evaluation? Year Via PUF2020 GSA Forum "Via PUF Technology as a Root of Trust in IoT Supply Chain" https://www.gsaglobal.org/forums/via-puf-technology-as-a-root-of-trust-in-iot-supply-chain Fully Electronic Implicit Intrinsic 2015 Delay PUF 2002 SRAM PUF 2007 Metal resistance PUF 2009 Bistable Ring PUF 2011 DRAM PUF 2015 Digital PUF 2016 Oxide Rupture PUF 2018 Coating PUF Explicit Extrinsic 2006 Quantum Electronic PUF 2015 Optical PUFR. Pappu, "Physical One-Way Functions", PhD Thesis, MIT, 2001. Physical One-Way Functions. Optical 2002 Quantum Optical PUF 2017,2021 RF PUF RF 2002 Magnetic PUF Magnetic Implicit 1994

Electronic-measurement PUFs

Implicit randomness

Via PUF The Via PUF technology is based on "via" or "contact" formation during the standard CMOS fabrication process. The technology is the outcome of the reverse thinking process. Rather than meeting the design rules, it makes the sizes of Via or Contact be smaller than the requirements in a controlled manner, resulting in unpredictable or stochastic formation of Via or Contact, i.e. 50% probability of making the electrical connection. The technology details are published in 2020 for the first time while the technology is already in mass production in 2015 by ICTK. Few characteristics of Via PUF are followings: Reliability: Thanks to the metallic property, once "via" or "contact" are formed in a structure, they stay there nearly permanently regardless of PVT variation, which means 0% of bit error rate and thus the post processing stages such as error correction code or helper data algorithm are not required. The technology is verified by the JEDEC standard tests and passed the Automotive Electronics Council Q-100 Grade 3 test for automotive applications. Randomness of the Via PUF achieves 0.4972 of Hamming weight closed to the ideal value of 0.5. The technology passed NIST Special Publication 800-92 and NIST SP 800-90B randomness tests. Uniqueness and ‘InbornID’: Uniqueness is an important property of PUF since it would guarantee that one chip ID is always different from other chips. The Via PUF reports 0.4999 of Hamming Distance value closed to the ideal uniqueness of 0.5. The 'InbornID' of the Via PUF stands for on-chip unique ‘inborn’ ID of a silicon chip. Obscurity is one of the great advantages of using the Via PUF technology in IC implementation. The Via or Contact holes of PUF are scattered around all over the chip. No need to form array blocks like the SRAM PUF. Practically impossible to distinguish PUF Vias from regular logic Vias, making IC reverse engineering almost impossible. Standard Manufacturing Process: The Via PUF technology uses standard cell structures from standard digital library with regular core voltage. No high voltage, and so no special circuitry like charge pump. There is no extra mask layer required in the IC manufacturing process. The Via PUF based Hardware RoT (Root of Trust) chips are currently applied in various markets such as telecommunications, appliances, and IoT devices in the forms of Wifi/BLE modules, smart door locks, IP cameras, IR sensor hub, etc. The technology supports the security functionalities such as anti-counterfeiting, secure boot, secure firmware copy protection, secure firmware update and secure data integrity.

Delay PUF

A delay PUF exploits the random variations in delays of wires and gates on silicon. Given an input challenge, a race condition is set up in the circuit, and two transitions that propagate along different paths are compared to see which comes first. An arbiter, typically implemented as a latch, produces a 1 or a 0, depending on which transition comes first. Many circuits realizations are possible and at least two have been fabricated. When a circuit with the same layout mask is fabricated on different chips, the logic function implemented by the circuit is different for each chip due to the random variations of delays.

A PUF based on a delay loop, i.e., a ring oscillator with logic, in the publication that introduced the PUF acronym and the first integrated PUF of any type. A multiplexor-based PUF has been described, as has a secure processor design using a PUF and a multiplexor-based PUF with an RF interface for use in RFID anti-counterfeiting applications.S. Devadas, V. Khandelwal, S. Paral, R. Sowell, E. Suh, T. Ziola, Design and Implementation of `Unclonable' RFID ICs for Anti-Counterfeiting and Security Applications, RFID World 2008, March 2008

SRAM PUF

These PUFs use the randomness in the power-up behavior of standard static random-access memory on a chip as a PUF. The use of SRAM as a PUF was introduced in 2007 simultaneously by researchers at the Philips High Tech Campus and at the University of Massachusetts. Since the SRAM PUF can be connected directly to standard digital circuitry embedded on the same chip, they can be immediately deployed as a hardware block in cryptographic implementations, making them of particular interest for security solutions. SRAM-based PUF technology has been investigated extensively. Several research papers explore SRAM-based PUF technology on topics such as behavior, implementation, or application for anti-counterfeiting purposes.Christoph Böhm, Maximilian Hofer, "Using SRAMs as Physical Unclonable Functions", Austrochip – Workshop on Microelectronics, Oct 7, 2009, Graz, Austria Notable is the implementation of secure secret key storage without storing the key in digital form. SRAM PUF-based cryptographic implementations have been commercialized by Intrinsic ID,Intrinsic ID company website a spin-out of Philips, and as of 2019, are available on every technology node from 350 nm down to 7 nm. Intrinsic ID was acquired by electronic design automation software and silicon IP company Synopsys in 2024.Synopsys buys Intrinsic-ID for PUF security

Due to deep submicron manufacturing process variations, every transistor in an Integrated Circuit (IC) has slightly different physical properties. These lead to small differences in electronic properties, such as transistor threshold voltages and gain factor. The start-up behavior of an SRAM cell depends on the difference of the threshold voltages of its transistors and other transistor parameters. An SRAM cell has two stable states, which normally represent the zero and one logical states. If the transistors of an SRAM cell were identical, the cell will be perfectly balanced and it will randomly start into one of the two stable states. However, even the smallest differences between transistor parameters will create a cell imbalance and will push the SRAM cell into one of the two stable states with a higher probability than the other state. Given that most SRAM cells have its own preferred state every time they are powered, from an SRAM array of cells a unique and random pattern of zeros and ones can be obtained. This pattern is like a chip's fingerprint, since it is unique to a particular SRAM and hence to a particular chip.

Post-processing of SRAM PUF