Hexagon is the brand name for a family of digital signal processor (DSP) and later neural processing unit (NPU) products by Qualcomm. Hexagon is also known as QDSP6, standing for “sixth generation digital signal processor.” According to Qualcomm, the Hexagon architecture is designed to deliver performance with low power over a variety of applications.

Each version of Hexagon has an instruction set and a micro-architecture. These two features are intimately related.

Hexagon is used in Qualcomm Snapdragon chips, for example in smartphones, cars, wearable devices and other mobile devices and is also used in components of cellular phone networks.

Instruction set architecture Computing devices have instruction sets, which are their lowest, most primitive languages. Common instructions are those which cause two numbers to be added, multiplied or combined in other ways, as well as instructions that direct the processor where to look in memory for its next instruction. There are many other types of instructions.

Assemblers and compilers that translate computer programs into streams of instructions – bit streams - that the device can understand and carry out (execute). As an instruction stream executes, the integrity of system function is supported by the use of instruction privilege levels. Privileged instructions have access to more resources in the device, including memory. Hexagon supports privilege levels.

Originally, Hexagon instructions operated on integer numbers but not floating point numbers, but in v5 floating point support was added.

The processing unit which handles execution of instructions is capable of in-order dispatching up to 4 instructions (the packet) to 4 execution units every clock.Porting LLVM to a Next Generation DSP, L. Taylor Simpson (Qualcomm) // LLVM Developers’ Meeting: 11/18/2011

Micro-architecture Micro-architecture is the physical structure of a chip or chip component that makes it possible for a device to carry out the instructions. A given instruction set can be implemented by a variety of micro-architectures. The buses – data transfer channels – for Hexagon devices are 32 bits wide. That is, 32 bits of data can be moved from one part of the chip to another in a single step. The Hexagon micro-architecture is multi-threaded, which means that it can simultaneously process more than one stream of instructions, enhancing data processing speed. Hexagon supports very long instruction words, which are groupings of four instructions that can be executed “in parallel.” Parallel execution means that multiple instructions can run simultaneously without one instruction having to complete before the next one starts. The Hexagon micro-architecture supports single instruction, multiple data operations, which means that when a Hexagon device receives an instruction, it can carry out the operation on more than one piece of data at the same time.

According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its system on a chip (SoCs) (average 2.3 DSP core per SoC) in 2011, and 1.5 billion cores were planned for 2012, making the QDSP6 the most shipped architecture of DSPWill Strauss, Forward Concepts. Wireless/DSP Market Bulletin: Qualcomm Leads in Global DSP Silicon Shipments // Forward Concepts: "In calendar year 2011, Qualcomm shipped a reported 521 million MSM chip shipments and we estimate that an average of 2.3 of its DSP cores in each unit resulted in 1.2 billion DSPs shipped in silicon. This (calendar) year, we estimate that the company will ship an average of 2.4 DSP cores with each (more complex) MSM chip." (CEVA had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licensable DSP market; ; , 2012).

The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, very long instruction word (VLIW), single instruction, multiple data (SIMD),Hexagon v2 Programmers Reference and instructions geared toward efficient signal processing. Hardware multithreading is implemented as barrel temporal multithreading - threads are switched in round-robin fashion each cycle, so the 600 MHz physical core is presented as three logical 200 MHz cores before V5.Faster 128-EEA3 and 128-EIA3 Software, Roberto Avanzi and Billy Bob Brumley (Qualcomm Research), Cryptology ePrint Archive: Report 2013/428, 2 Jul 2013. Page 9. Hexagon V5 switched to dynamic multithreading (DMT) with thread switch on L2 misses, interrupt waiting or on special instructions.Qualcomm Extends Hexagon DSP: Hexagon v5 Adds Floating-Point Math, Dynamic Multithreading // Linley Gwennap, Microprocessor Report, August 2013

At Hot Chips 2013 Qualcomm announced details of their Hexagon 680 DSP. Qualcomm announced Hexagon Vector Extensions (HVX). HVX is designed to allow significant compute workloads for advanced imaging and computer vision to be processed on the DSP instead of the CPU. In March 2015 Qualcomm announced their Snapdragon Neural Processing Engine SDK which allow AI acceleration using the CPU, GPU and Hexagon DSP.

Qualcomm's Snapdragon 855 contains their 4th generation on-device AI engine, which includes the Hexagon 690 DSP and Hexagon Tensor Accelerator (HTA) for AI acceleration. Snapdragon 865 contains the 5th generation on-device AI engine based on the Hexagon 698 DSP capable of 15 trillion operations per second (TOPS). Snapdragon 888 contains the 6th generation on-device AI engine based on the Hexagon 780 DSP capable of 26 TOPS. Snapdragon 8 contains the 7th generation on-device AI engine based on the Hexagon DSP capable of 52 TOPS and up to 104 TOPS in some cases.

Software support Operating systems The port of Linux for Hexagon runs under a hypervisor layer ("Hexagon Virtual Machine"https://docs.qualcomm.com/bundle/publicresource/80-NB419-3_REV_A_Hexagin_Virtual_Machine_Specification.pdf (restricted access)) and was merged with the 3.2 release of the kernel.Linux Kernel 3.2 Release Notes "1.4. New architecture: Hexagon" The original hypervisor is closed-source, and in April 2013 a minimal open-source hypervisor implementation for QDSP6 V2 and V3, the "Hexagon MiniVM" was released by Qualcomm under a BSD-style license.Richard Kuo, Hexagon MiniVM // linux.ports.hexagon, 25 Apr 2013Hexagon MiniVM // CodeAurora (Qualcomm)

Compilers Support for Hexagon was added in 3.1 release of LLVM by Tony Linthicum. Hexagon/HVX V66 ISA support was added in 8.0.0 release of LLVM. There is also a non-FSF maintained branch of GCC and binutils.

Adoption of the SIP block Qualcomm Hexagon DSPs have been available in Qualcomm Snapdragon SoC since 2006.Qualcomm Announces Its 2012 Superchip: 28nm Snapdragon S4, 10/12/2011 by John Oram. Quote: "Hexagon DSPs have been in Snapdragon chips since 2006."QDSP6 V4: Qualcomm Gives Customers and Developers Programming Access to its DSP Core // InsideDSP, June 22, 2012 In Snapdragon S4 (MSM8960 and newer) there are three QDSP cores, two in the Modem subsystem and one Hexagon core in the Multimedia subsystem. Modem cores are programmed by Qualcomm only, and only Multimedia core is allowed to be programmed by user.

They are also used in some femtocell processors of Qualcomm, including FSM98xx, FSM99xx and FSM90xx.Qualcomm Aims Hexagon at Femtocells, October 31, 2011. Linley Gwennap// Linley WIRE

Third-party integration In March 2016, it was announced that semiconductor company Conexant's AudioSmart audio processing software was being integrated into Qualcomm's Hexagon.

In May 2018 wolfSSL added support for using Qualcomm Hexagon. This is support for running wolfSSL crypto operations on the DSP. In addition to use of crypto operations a specialized operation load management library was later added.

Versions There are six versions of QDSP6 architecture released: V1 (2006), V2 (2007–2008), V3 (2009), V4 (2010–2011), QDSP6 V5 (2013, in Snapdragon 800), and QDSP6 V6 (2016, in Snapdragon 820) V4 has 20 DMIPS per milliwatt, operating at 500 MHz.

Clock speed of Hexagon varies in 400–2000 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5.

Versions of QDSP6(DSP/NPU) Process node, nm Year Number of simultaneous threads Per-thread clock, MHz Total core clock, MHz Product QDSP6 V1 65 2006 QDSP6 V2QDSP6 V4: BDTI Benchmark Results and Implementation Details Of Qualcomm's DSP Core // BDTI, February 12, 2013 65 2007 6 100 600 QDSP6 V3 (1st gen) 45 2009 6 67 400 QDSP6 V3 (2nd gen) 45 2009 4 100 400 QDSP6 V4 (V4M, V4C, V4L) 28 2010 3 167 500 Snapdragon 600 QDSP6 V5Qualcomm's QDSP6 v5: Benchmarking Results Confirm That Floating-Point Support Has Arrived // BDTI, June 12, 2013 (V5A, V5H) 28 2013 3 200 or greater with DMT 600 Snapdragon 410/412/800/801 536 12/28 2014 205/208/210/212 Snapdragon 425/427/429/430/435/439 V50 (or QDSP6 V5.0) 28 2014 700/800 (805) Snapdragon 415/610/615/616/805 546 14/28 2015 Snapdragon 450/617/625/626/632 V56 (or QDSP6 V5.6) 20/28 2015 800 (808/810) Snapdragon 650/652/653/808/810 642 14 2017 Snapdragon 630 680 (or QDSP6 V6) 14 2016 4 500 787 (660), 2000 (820Qualcomm's QDSP6 v6: Imaging and Vision Enhancements Via Vector Extensions // BDTI, September 29, 2015 & 821) Snapdragon 636/660/820/821 682 10 2017Snapdragon 835 683 11 2020 Snapdragon 460/662 685 10/11 2018 (3 TOPS) Snapdragon 670/675/678/710/712/845/850 686 6/8/11 2019 (3.3 TOPS) Snapdragon 480/480+/665/680/685/695 688 8 2019 (3.6 TOPS) Snapdragon 730/730G/732G 690 7 2019 (7 TOPS/9 TOPS) Snapdragon 855/855+/860/8c/8cx/8cx Gen 2 Microsoft SQ1/SQ2 692 8 2020 (5 TOPS) Snapdragon 690/720G/7c/7c Gen 2 694 8 2020 (4.7 TOPS) Snapdragon 750G 696 7 2020 (5.4 TOPS) Snapdragon 765/765G/768G 698 7 2020 (15 TOPS) Snapdragon 865/865+/870/8cx Gen 3 Microsoft SQ3 770 5/6 2021 (12 TOPS) Snapdragon 778G/778G+/780G/782G 780 5 2021 (26 TOPS/32 TOPS) Snapdragon 888/888+ 790 (NPU/HTP) 4 2021 (32 TOPS)(INT8) Snapdragon 8 Gen 1/8+ Gen 1 NPU (HTP Gen 2) 4 2022 (26 TOPS)(INT8) Snapdragon 8 Gen 2 NPU (HTP Gen 3) 4 2023 (34 TOPS)(INT8) Snapdragon 8 Gen 3/8s Gen 3 NPU (HTP Gen 4) 3 2024 (50 TOPS)(INT8) Snapdragon 8 Elite NPU (HTP Gen 4) 4 2024 (45 TOPS) (INT8) Snapdragon X (Plus/Elite)

Availability in Snapdragon products Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table.

QDSP5 usage:

Snapdragon generation Chipset (SoC) ID DSP generation DSP frequency, MHz Process node, nm S1 MSM7627, MSM7227, MSM7625, MSM7225 QDSP5 320 65 S1 MSM7627A, MSM7227A, MSM7625A, MSM7225A QDSP5 350 45 S2 MSM8655, MSM8255, APQ8055, MSM7630, MSM7230 QDSP5 256 45 S4 Play MSM8625, MSM8225 QDSP5 350 45 S200Snapdragon 800, 600, 400, 200 Processor Specs // Qualcomm 8110, 8210, 8610, 8112, 8212, 8612, 8225Q, 8625Q QDSP5 384 45 LP

QDSP6 (Hexagon) usage:

Snapdragon generation Chipset (SoC) ID QDSP6 version DSP frequency, MHz Process node, nm S1 QSD8650, QSD8250 QDSP6 600 65 S3 MSM8660, MSM8260, APQ8060 QDSP6 (V3?) 400 45 S4 Prime MPQ8064 QDSP6 (V3?) 500 28 S4 Pro MSM8960 Pro, APQ8064 QDSP6 (V3?) 500 28 S4 Plus MSM8960, MSM8660A, MSM8260A, APQ8060A, MSM8930, MSM8630, MSM8230, APQ8030, MSM8627, MSM8227 QDSP6 (V3?) 500 28 S400 8926, 8930, 8230, 8630, 8930AB, 8230AB, 8630AB, 8030AB, 8226, 8626 QDSP6V4 500 28 LP S600 8064T, 8064M QDSP6V4 500 28 LP S800 8974, 8274, 8674, 8074 QDSP6V5A 600 28 HPm S820 8996 QDSP6V6 2000 14 FinFET LPP

Hardware codec supported The different video codecs supported by the Snapdragon SoCs.

D - decode; E - encode

FHD = FullHD = 1080p = 1920x1080px

HD = 720p which can be 1366x768px or 1280x720px

Snapdragon 200 series The different video codecs supported by the Snapdragon 200 series. Codec Snapdragon 200 Snapdragon 200 Qualcomm 205 Snapdragon 208/210 Snapdragon