ICT 1900 was a family of mainframe computers released by International Computers and Tabulators (ICT) and later International Computers Limited (ICL) during the 1960s and 1970s. The 1900 series was notable for being one of the few non-American competitors to the IBM System/360, enjoying significant success in the European and British Commonwealth markets.

Origins

In early 1963, ICT was engaged in negotiations to buy the computer business of Ferranti. In order to sweeten the deal, Ferranti demonstrated to ICT the Ferranti-Packard 6000 (FP6000) machine, which had been developed by its Canadian subsidiary Ferranti-Packard, to a design known as Harriac that had been initiated in Ferranti by Harry Johnson and fleshed out by Stanley Gill and John Iliffe.

The FP6000 was an advanced design, notably including hardware support for multiprogramming. ICT considered using the FP6000 as their medium-sized processor in the 1965–1968 timeframe, replacing the ICT 1302. Another plan being considered was to license a new range of machines being developed by RCA, probably compatible with the expected IBM 8000.

On 7 April 1964 IBM announced the System/360 series, a family of compatible machines spanning nearly the complete range of customer needs. It was immediately obvious that ICT would need a coherent response. Two paths were available: develop a range of machines based on the FP6000, using the flexibility of its design to produce smaller or larger machines, or cooperate with RCA who were re-targeting their development to a System/360 compatible range to be known as the RCA Spectra 70.

One major consideration was that the FP6000 was already running, while the RCA Spectra range would take some years to become available. In the end, the decision was made to go with a range of machines based on the FP6000. The centrepiece of the new range was the ICT 1904, a version of the FP6000 with the ICT standard peripheral interface. For higher-end machines, a new larger processor, the ICT 1906, was to be developed by the ICT West Gorton unit (formerly part of Ferranti). To meet the needs of smaller customers, smaller machines, the ICT 1901 and ICT 1902/3, were developed by the ICT Stevenage unit, based on the PF182 and PF183 processors already in development.

On 29 September 1964 the ICT 1900 range was announced in a filmed presentation, scripted by Antony Jay. The following week two working systems were demonstrated at the Business Equipment Exhibition, Olympia.

The first commercial sale was made in 1964 to the Morgan Crucible Company, comprising a 16K word 1902 with an 80-column 980-card/minute reader, a card punch, a 600 line/min printer and 4 x 20kchar/s tape drives. It was soon upgraded to a 32K word memory and a floating point unit to allow for some scientific work. The same company had also been the first to order ICT's first computer, the HEC4 (later ICT 1201), in 1955.

The first system delivered was a 1904, for the Northampton College of Advanced Technology, London, in January 1965.

Architecture

The ICT 1900 was a word-addressing machine using a register-to-memory architecture with eight accumulator registers, three of which could be used as modifier (index) registers. The word length was 24 bits, which could be used as four six-bit characters; instructions were provided for copying single characters to and from memory.

The accumulators were addressable as if they were the first eight words of memory, giving the effect of register-to-register instructions with no extra operation codes being needed. The hardware registers were an optional feature, and if not fitted the accumulators were the first eight words of memory. The large number of optional features in the FP6000 design gave ICT great flexibility in pricing.

A notable feature of the series was the hardware support (in all except the smallest processors) for running multiple processes – every process ran in an independent address space, enforced by datum and limit registers. No user process could access the memory of any other process. Later models added paging hardware, allowing true virtual memory with the GEORGE 4 operating system.

On the original models the address size was 15 bits, allowing up to 32K words of memory. Later models added 22-bit addressing, allowing a theoretical 4Mword maximum memory. Instructions contained a 12-bit operand, either fixed or offset from an index register. Branch instructions held a 15-bit offset, allowing access to all memory on the initial range. When the address size was increased to 22 bits, replaced (indirect) and relative branches were added to the instruction set to allow access to the larger address space.

The largest change between the original FP6000 and the 1900 series was the inclusion of the ICT standard interface for connection of peripherals. This allowed connection of any ICT peripheral to any processor of the series, and owners could upgrade their processors while keeping the same peripherals or vice versa.

All I/O operations were initiated by a privileged supervisor process, known as the executive. User processes communicated with the executive using extracodes, instructions that caused a trap into the executive. The executive would then communicate with the appropriate peripheral via the Standard Interface, using functions not available to user processes. The subsequent data transfers would then occur across this interface, autonomously without further program involvement. The conclusion of the transfers (or error if any) would similarly be indicated back to the executive.

On smaller members of the series, some expensive instructions (floating point for example) were also implemented as extracodes. The combination of the executive and hardware provided the same interface to programs running on any model of the range.

The hardware floating-point unit, if fitted, ran autonomously. After a floating-point operation was started, integer instructions could be run in parallel until the result of the floating-point operation was needed.

Data formats

The instruction set supported the following data formats:

Characters A 24-bit word could hold four six-bit characters. Counter modifier, also known as an index word A 9-bit counter and a 15-bit modifier (address) field. A loop instruction decremented the counter and incremented the address either by 1 or 2. This format was only available in 15-bit addressing mode. In 22-bit mode the counter and address were kept in separate words. Character counter modifier, also known as a character index word Two-bit character offset, seven-bit counter and 15-bit modifier (word address). The BCHX (branch on character indexing) instruction decremented the counter and incremented the character offset, incrementing the word address if the character offset overflowed, branching if the count had not reached zero. In 22-bit addressing mode the counter was unavailable, and the format was a two-bit character offset and a 22-bit word address. The BCHX instruction incremented the character offset, incremented the word address if the character offset overflowed, and branched unconditionally. Single-length integer A 24-bit two's complement signed number. Multi-length integer The first word held a 24-bit two's complement signed number, subsequent words held 23-bit extensions with the high bit used for internal carry. Single-length floating point number Two words holding a 24-bit signed argument (mantissa) and a nine-bit exponent. Double-length floating-point number Two words holding a 38-bit signed argument and a nine-bit exponent. Quadruple-length floating-point number Four words holding a 75-bit signed argument and a nine-bit exponent. Handled in software on all but 1906/7 processors with the extended floating-point feature.

Character sets

Since the ICT 1900 used a six-bit character it was largely limited to a 64-character repertoire, with only upper case letters and no control characters.

In order to deal with data on paper tape or from communications equipment, a system of shifts could be used to represent the full 128 characters of ASCII. Character #74 (i.e. octal 74) was considered an alpha shift and indicated subsequent characters were to be considered uppercase, #75 was a beta shift and indicated subsequent characters were in lower case, and #76 the delta shift, indicating the next character was a control character. Thus the ASCII string "Hello World" would be encoded as "αHβELLO αWβORLD". Character #77 was a fill (ignore) character, similar to the rubout character in the 7-bit world.

The 1900 used a variant of ASCII-63, known by ICT as the ECMA character set, with differences in five character codes:

ASCII $ \ ^ _ ` ECMA £ $ ↑ ← _

Comparison with System/360

Both the 1900 series and IBM System/360 provided hardware support for multi-programming. On the 1900, all user memory addresses were modified by a datum (base address) register and checked against a limit register (base and bounds), preventing one program interfering with another. The System/360 gave each process and every 2048-byte block of memory a four-bit key, and if a process key did not match the memory block key an exception would result. The 1900 system required programs to occupy a contiguous area of memory but allowed processes to be relocated during execution, simplifying the work of the operating system. The 1900 also allowed any process direct access to the first 4096 words of its address space. (Both the 1900 and 360 had a 12-bit operand field, but on the 360 addresses were physical addresses so a program could directly access the first 4096 bytes of physical memory).

The System/360 had the advantage of a larger word and character size; its 32-bit words were large enough for (low accuracy) floating point numbers whereas the 1900 needed at least two words. The eight-bit byte of the System/360 allowed manipulation of lowercase characters without the complex shift sequences of the 1900. However, in the early days the smaller word size of the 1900 was seen as a cost advantage, as the memory could be 25% cheaper for the same number of words.

1900 range

Initial range

The initial range of machines was:

ICT 1901 A very small machine with a 6-bit wide mill (arithmetic unit). For compatibility with the other machines a 24-bit operation was performed by the processor as four 6-bit operations. Based on the PF183 developed by ICT Stevenage. The 1901 was announced and released after the other members of the initial range, in response to the IBM System/360 Model 20, and was a great success. ICT 1902 A small machine. Based on the ICT Stevenage PF182 processor. Like the 1901, the 1902 performed multiply and divide operations as extracodes. An optional commercial computing facility or CCF was available to add hardware multiply and divide. An optional floating point unit, the scientific computing facility, SCF was also available as a super-set of the CCF. ICT 1903 The same processor as the 1902, but with 2μs core in place of the 6μs core supplied with the 1902. ICT 1904 The ICT West Gorton processor derived from the FP6000 with the addition of the ICT standard interface. ICT 1905 A 1904 with an autonomous hardware floating point unit. ICT 1906 A new processor designed by ICT West Gorton with a 48-bit wide memory pathway and a 22-bit addressing mode. Delivered with up to 256Kwords of memory. ICT 1907 A 1906 with a floating point unit. ICT 1909 A machine similar to the 1905 but with a slow 6μs store comparable to the 1902. Designed for universities who needed floating point but found the 1905 too expensive.

The execution time for an addition instruction ("add the contents of store location x to register y") ranged from 2.5 μs for a 1906 or 1907 with 1.1 μs core store, to 34 μs for a 1901 with 6 μs core store.