The IBM System/360 architecture is the model independent architecture for the entire S/360 line of mainframe computers, including but not limited to the instruction set architecture. The elements of the architecture are documented in the IBM System/360 Principles of Operation and the IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information manuals.

Features IBM S/360 registers+ General Registers 0-15 Two's complement value 0 31+ Floating Point Registers 0, 2, 4 and 6 S Biased exponent Mantissa 0 1 7 8 31 Mantissa (continued) 32 63+ S/360 PSW Chan.Mask IO EX Key A M W P Interruption Code 0 1 2 4 5 6 7 8 11 12 13 14 15 16 31 ILC CC ProgramMask Instruction Address 32 33 34 35 36 39 40 63+ Bits Field Meaning 0-5 Channel Masks for channels 0-5 6 IO I/O Mask for channels > 5 7 EX External Mask 8-11 Key PSW key 12 A ASCII mode for decimal arithmetic 13 M Machine-check mask 14 W Wait state 15 P Problem state 16-31 IC Interruption Code 32-33 ILC Instruction-Length Code 34-35 CC Condition Code 36-39 PM Bit Meaning 36 Fixed-point overflow 37 Decimal overflow 38 Exponent underflow 39 Significance 40-63 IA Instruction Address IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0.

The System/360 architecture provides the following features: 16 32-bit general-purpose registers 4 64-bit floating-point registers 64-bit processor status register (PSW), which includes a 24-bit instruction address 24-bit (16 MB) byte-addressable memory space Big-endian byte/word order A standard instruction set, including fixed-point binary arithmetic and logical instructions, present on all System/360 models (except the Model 20, see below). A commercial instruction set, adding decimal arithmetic instructions, is optional on some models, as is a scientific instruction set, which adds floating-point instructions. The universal instruction set includes all of the above plus the storage protection instructions and is standard for some models. The Model 44 provides a few unique instructions for data acquisition and real-time processing and is missing the storage-to-storage instructions. However, IBM offered a Commercial Instruction Set" feature that ran in bump storage and simulated the missing instructions. The Model 20 offers a stripped-down version of the standard instruction set, limited to eight general registers with halfword (16-bit) instructions only, plus the commercial instruction set, and unique instructions for input/output. The Model 67 includes some instructions to handle 32-bit addresses and "dynamic address translation", with additional privileged instructions to provide virtual memory.

Memory Memory (storage) in System/360 is addressed in terms of 8-bit bytes. Various instructions operate on larger units called halfword (2 bytes), fullword (4 bytes), doubleword (8 bytes), quad word (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as big-endian. Many uses for these units require aligning them on the corresponding boundaries. Within this article the unqualified term word refers to a fullword.

The original architecture of System/360 provided for up to 224 = 16,777,216 bytes of memory. The later Model 67 extended the architecture to allow up to 232 = 4,294,967,296 bytes of virtual memory.

Addressing System/360 uses truncated addressing similar to that of the UNIVAC III. That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15 general registers. In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses.

Data formats The S/360 architecture defines formats for characters, integers, decimal integers and hexadecimal floating point numbers. Character and integer instructions are mandatory, but decimal and floating point instructions are part of the Decimal arithmetic and Floating-point arithmetic features.

Characters are stored as 8-bit bytes. Integers are stored as two's complement binary halfword or fullword values. Packed decimal numbers are stored as 1 to 16 8-bit bytes containing an odd number of decimal digits followed by a 4-bit sign. Sign values of hexadecimal A, C, E, and F are positive and sign values of hexadecimal B and D are negative. Digit values of hexadecimal A-F and sign values of 0-9 are invalid, but the PACK and UNPK instructions do not test for validity. Zoned decimal numbers are stored as 1 to 16 8-bit bytes, each containing a zone in bits 0-3 and a digit in bits 4-7. The zone of the rightmost byte is interpreted as a sign. Floating point numbers are only stored as fullword or doubleword values on older models. On the 360/85 and 360/195 there are also extended precision floating point numbers stored as quadwords. For all three formats, bit 0 is a sign and bits 0-7 are a characteristic (exponent, biased by 64). Bits 8-31 (8-63) are a hexadecimal fraction. For extended precision, the low order doubleword has its own sign and characteristic, which are ignored on input and generated on output.

Instruction formats Instructions in the S/360 are two, four or six bytes in length, with the opcode in byte 0. Instructions have one of the following formats: RR (two bytes). Generally byte 1 specifies two 4-bit register numbers, but in some cases, e.g., SVC, byte 1 is a single 8-bit immediate field. RS (four bytes). Byte 1 specifies two register numbers; bytes 2-3 specify a base and displacement. RX (four bytes). Bits 0-3 of byte 1 specify either a register number or a modifier; bits 4-7 of byte 1 specify the number of the general register to be used as an index; bytes 2-3 specify a base and displacement. SI (four bytes). Byte 1 specifies an immediate field; bytes 2-3 specify a base and displacement. SS (six bytes). Byte 1 specifies two 4-bit length fields or one 8-bit length field; bytes 2-3 and 4-5 each specify a base and displacement. The encoding of the length fields is length-1.

Instructions must be on a two-byte boundary in memory; hence the low-order bit of the instruction address is always 0.

Program Status Word (PSW)

The Program Status Word (PSW) contains a variety of controls for the currently operating program. The 64-bit PSW describes (among other things) the address of the current instruction being executed, condition code and interrupt masks.

+ PSW format Bits Contents Explanation 0-7 System Mask bits 0-5: enable channels 0-5, bit 6: enable all remaining channels, bit 7: enable External interruptions (timer, interrupt key, and external signal 8-11 Protection key CPU protection key to compare against storage protection keys 12 ASCII mode enable ASCII mode for packed decimal instructions, never used by IBM software 13 Machine checks enable Machine check interruptions 14 Wait State processor is halted, an interruption, if enabled, will cause the processor to resume executing instructions 15 Problem state enable to prevent the use of instructions reserved for supervisor state 16-31 Interruption Code code to indicate the type of interruption, inserted when the PSW is stored, during IPLoad, this is the address of the device from which the program was loaded 32-33 Instruction Length Code length in halfwords or 0 if unavailable 34-35 Condition Code see individual instructions for encoding 36-39 Program Mask bit 36: enable fixed-point overflow, bit 37: decimal overflow, bit 38: exponent underflow, bit 39: significance40-63 Instruction Address address of next instruction, except for a program interruptions with ILC 0

Load Program Status Word (LPSW) is a privileged instruction that loads the Program Status Word (PSW), including the program mode, protection key, and the address of the next instruction to be executed. LPSW is often used to return from an interruption by loading the old PSW that is associated with the interruption class. One privileged instruction (SSM) and one unprivileged instruction (SPM) are available for manipulating subsets of the PSW without causing an interruption or loading a PSW.

Interruption system The architecture defines 5 classes of interruption. An interruption is a mechanism for automatically changing the program state; it is used for both synchronous and asynchronous events.

Interruption class Old PSW New PSW Priority hex dec hex dec Input/Output 38 56 78 120 4 Program 28 40 68 104 2 Supervisor Call 20 32 60 96 2 External 18 24 58 88 3 Machine Check 30 48 70 112 1

There are two storage fields assigned to each class of interruption on the S/360; an old PSW double-word and a new PSW double-word. The processor stores the PSW, with an interruption code inserted, into the old PSW location and then loads the PSW from the new PSW location. This generally replaces the instruction address, thereby effecting a branch, and (optionally) sets and/or resets other fields within the PSW, thereby effecting a mode change.

The S/360 architecture defines a priority to each interruption class, but it is only relevant when two interruptions occur simultaneously; an interruption routine can be interrupted by any other enabled interruption, including another occurrence of the initial interruption. For this reason, it is normal practice to specify all of the mask bits, with the exception of machine-check mask bit, as 0 for the "first-level" interruption handlers. "Second-level" interruption handlers are generally designed for stacked interruptions (multiple occurrences of interruptions of the same interruption class).

Input/Output interruption An I/O interruption occurs at the completion of a channel program, after fetching a CCW with the PCI bit set and also for asynchronous events detected by the device, control unit or channel, e.g., completion of a mechanical movement. The system stores the device address into the interruption code and stores channel status into the CSW at location 64 ('40'X).

Program interruption A Program interruption occurs when an instruction encounters one of 15 exceptions; however, if the Program Mask bit corresponding to an exception is 0 then there is no interruption for that exception. On 360/65, 360/67 and 360/85 the Protection Exception and Addressing Exception interruptions can be imprecise, in which case they store an Instruction Length Code of 0. The Interruption code may be any of

+ Interruption codes for Program interruptionsold PSW bits 26-31 hexbits 26-31 Dec Exception 0 0Imprecise interruption on 360/91, 360/95 or 360/195 + bit Exception 16 Protection 17 Addressing 18 Specification 19 Data 20 Fixed-Point Overflow 21 Fixed-Point Divide 22 Exponent Overflow 23 Exponent Underflow 24 Significance 25 Floating-Point Divide 26 Decimal Overflow 27 Decimal Divide 1 1 Operation 2 2 Privileged operation 3 3 Execute 4 4 Protection 5 5 Addressing 6 6 Specification 7 7 Data 8 8 Fixed-point overflow 9 9 Fixed-point divide A 10 Decimal overflow B 11 Decimal divide C 12 Exponent overflow D 13 Exponent underflow E 14 Significance F 15 Floating-point divide 10 16Segment Translation 11 17Page Translation 12 18SSM Exception

An operation exception is recognized when a program attempts to execute an instruction with an opcode that the computer does not implement. In particular, an operation exception is recognized when a program is written for an optional feature, e.g., floating point, that is not installed. A privileged operation exception is recognized when a program attempts to execute a privileged instruction when the problem state bit in the PSW is 1. An execute exception is recognized when the operand of an EXECUTE instruction (EX) is another EXECUTE instruction.