This article contains information about Intel's GPUs (see Intel Graphics Technology) and motherboard graphics chipsets in table form. In 1982, Intel licensed the NEC μPD7220 and announced it as the Intel 82720 Graphics Display Controller.
Gen1
Intel's first generation GPUs: Graphics Launch Market Chipset Code name DeviceID RAMDACclock (MHz) Pixel pipelines Shader model(vertex/pixel) API support Memory bandwidth (GB/s) DVMT (MB) Hardware acceleration Direct3D OpenGL OpenCL MPEG-2 VC-1 AVC i740 1998 Desktop stand-alone Auburn 7800 220 1 3.0 (SW) / No 5.0 1.1 rowspan=6 0.8 2–8 Optional external MPEG-2 decoder via Video Module Interface rowspan=6 rowspan=6 i752 1999 Portola 1240 250 6.0 (full) 8.0 (some features, no hardware shaders) 0.8(PC100)–1.067(PC133)1.067(AGP 4× for AIMM) 8–16 MC 3D graphicswithDirect AGP 810 Whitney 7121 230 32 810-DC100 7123 810E810E2 7125 2000 815815E8925G815EG Solano 1132 6.0 (full) 9.0 (some features, no hardware shaders)
Gen2 Intel marketed its second generation using the brand Extreme Graphics. These chips added support for texture combiners allowing support for OpenGL 1.3.
Graphics Launch Market Chipset Code name DeviceID Core renderclock (MHz) Pixel pipelines Shader model(vertex/pixel) API support Memory bandwidth (GB/s) DVMT (MB) Hardware acceleration Direct3D OpenGL OpenCL MPEG-2 VC-1 AVC ExtremeGraphics 2002 Desktop 845G845GE845GL845GV Brookdale 2562 200 2 3.0 (SW) / No 6.0 (full)9.0 (some features, no hardware shaders) 1.3 ES 1.1Linux rowspan=6 2.1 64 MC rowspan=6 rowspan=6 2001 Mobile 830M830MG Almador 3577 166Intel 830 Chipset Family: 82830 Graphics and Memory Controller Hub (GMCH-M) Datasheet, Order Number 298338-003, January 2002 (section 5.8 "Clocking") 1 ExtremeGraphics 2 2003 Desktop 865G865GV Springdale 2572 266 6.4 Mobile 852GM852GME852GMV Montara 3582 133–266 2.1–2.7 854 358E 855GM 855GME 3582
Gen3 Intel's first DirectX 9 GPUs with hardware Pixel Shader 2.0 support. Graphics Launch Market ChipsetDeviceIDPixel pipelinesClock rateMemoryAPI support Hardware accelerationCode nameNameDVMT (MB)Bandwidth (GB/s)Shader model(vertex/pixel) Direct3D OpenGL OpenCL MPEG-2 VC-1 AVC GMA 900 2004 Desktop Grantsdale 910GL 2582 258A 4 333 128 3.2 3.0 (SW) / 2.0 6.0 (full) 9.0 (partial; no WDDM nor Aero support) 1.4 2.1Linux ES 2.0Linux rowspan=15 MC rowspan=15 rowspan=15 915GL 915GV 8.5 915G 2005 Mobile Alviso Mobile 915Family 2592 133–333 GMA 950 Desktop Lakeport 945GZ 2772 400 256 9.0c FL9_1 945GC 10.7 945G 2006 Mobile Calistoga Mobile 945Family 27A227AE 166–400 GMA 3100 2007 Desktop Bearlake Q33 29D2 400 12.8 Q35 29B2 G31 29C2 G33 12.8 (DDR2)17 (DDR3) Variable-Length Decoding (VLD) + iDCT + MC (Full) GMA 3150 2010 Nettop Pineview Atom D4xxAtom D5xx A001 2 384 6.4 Netbook Atom N4xxAtom N5xx A011 200 5.3
Gen4 The last generation of motherboard integrated graphics. Full hardware DirectX 10 support starting with GMA X3500. Each EU has a 128-bit wide FPU that natively executes four 32-bit operations per clock cycle. Graphics Launch Market Code name ChipsetDeviceID Core renderclock (MHz) Execution units Shader model(vertex/pixel) API support Memorybandwidth (GB/s) DVMT (MB) Hardware accelerationDirect3D OpenGL OpenCL MPEG-2 VC-1 AVC GMA 3000 2006 Desktop Lakeport 946GZ 2972 667 8 3.0 (SW) / 2.0 9.0c FL9_1 1.4 2.1Linux ES 2.0Linux rowspan=20 10.6 256 MC rowspan=3 rowspan=9 BroadwaterQ963 2992Q965 12.8GMA X3000 G965 29A2 3.0 1.5 2.1Linux ES 2.0Linux 384 Full MC + (LF −WMV9 only)GMA X3500 2007 Bearlake G35 2982 4.0 10.0 FL10_0 2.1 ES 2.0Linux MC + LF GMA X3100 Mobile Crestline GL960 2A022A12 400 8.5 MC + (LF −WMV9 only)GLE960GM965 500 10.7GME965 GMA 4500 2008 Desktop Eaglelake B43 2E422E92 533 10 12.8 (DDR2)17 (DDR3) 1720 MC + LF MC + LFQ43 2E12Q45 GMA X4500 G41 2E32 800G43 2E22GMA X4500HD G45 Full Full GMA 4500MHD Mobile Cantiga GL40 2A42 400 GS40GM45 533 GS45GM47640
Gen5
Integrated graphics chip moved from motherboard into the processor. Improved gaming performance Can access CPU's cache Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle. Hierarchical-Z compression and fast Z clear
+ Specifications of Intel Gen5 graphics processing units Name Launch Market Processor DeviceID Executionunits Core clock(MHz) Memory API support Intel ClearVideo HD Code name Model DVMT(MB) Bandwidth(GB/s) Direct3D OpenGL OpenCL HD Graphics 2010 Desktop Ironlake (Clarkdale) Celeron G11010042 12 533 1720 17 10.1FL10_0 2.1ES 2.0Linux rowspan="23" rowspan="2" Core i3-5x0 733 21.3 YesCore i5-6x0Core i5-655K Core i5-661 900 Laptop Ironlake (Arrandale) Celeron U3xxx0046 166–500 12.8 rowspan="2" Pentium U5xxx Core i3-3x0UM YesCore i5-5x0UMCore i7-6x0UECore i7-6x0UM Core i7-620LE 266–566 17.1Core i7-6x0LM Celeron P4xxx 500–667 rowspan="2" Pentium P6xxxCore i3-330E YesCore i3-3x0M Core i5-4x0M 500–766Core i5-520ECore i5-5x0MCore i7-610ECore i7-6x0M
Gen6
Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle. Double peak performance per clock cycle compared to previous generation due to fused multiply-add instruction. The entire GPU shares a sampler and an ROP.
+ Specifications of Intel HD Graphics series Graphics Launch Market Processor Code name Device id. Core clock (MHz) Execution units API support Memory bandwidth(GB/s) DVMT (MB) QSVDirect3D OpenGL OpenCL HD Graphics 2011 Mobile Celeron B7x0Celeron 7x7Celeron 8x7Celeron B8xxPentium B9x0Pentium 9x7 Sandy Bridge 010A 350–1150 6(GT1) 10.1 11.1Windows 8+ FL10_1 3.1Windows 3.3macOS 3.3Linux ES 3.0Linuxrowspan=7 21.3 1720rowspan=2 Desktop Celeron G4x0Celeron G5x0Celeron G530TPentium G6xxPentium G6x0TPentium G8x0 650–1100 HD Graphics 2000 Desktop Core i3-2102Core i3-21x0Core i3-21x0TCore i5-2xx0Core i5-2x00SCore i5-2xx0TCore i7-2600Core i7-2600S 0102 650–1350 YesWorkstation Xeon E3-1260L HD Graphics 3000 Mobile Core i3-23x0ECore i3-23xxMCore i5-251xECore i5-2xxxMCore i7-2xxxMCore i7-2xxxQMCore i7-271xQECore i7-29x0XM 01160126 650–1300 12(GT2) Desktop Core i3-21x5Core i5-2405SCore i5-2500KCore i7-2x00K 01120122 850–1350HD Graphics P3000 Workstation Xeon E3-12x5 850–1350
Gen7
1 FP32 ALUs : EUs : Subslices Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions. Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.
{| class="wikitable sortable mw-datatable sticky-header-multi sort-under" style="text-align:center;" |+ Specifications of Intel HD Graphics series |- ! rowspan="2" style="width:7%" | Graphics ! rowspan="2" | Launch ! rowspan="2" | Market ! rowspan="2" | Processor ! rowspan="2" | Code name ! rowspan="2" | Device ID ! rowspan="2" | Core clock (MHz) ! rowspan="2" | Core config1 ! colspan="4" | API support ! rowspan="2" | Memory bandwidth(GB/s) ! rowspan="2" | DVMT (MB) ! rowspan="2" | QSV
! Direct3D || OpenGL || OpenCL || Vulkan
| rowspan="2" | HD Graphics | rowspan="17" | 2012 | Desktop | Celeron G16x0 Celeron G1610T Pentium G2xx0 Pentium G2xx0T | rowspan="17" | Ivy Bridge | rowspan="2" | 015A | 650–1050 | rowspan="4" | 48:6:1 (GT1) | rowspan="17" | 11.1 FL11_0 | rowspan="17" | 4.0Windows 4.1macOS 4.2Linux ES 3.0Linux | rowspan="17" | 1.2 | rowspan="17" | 1.0Linux | rowspan="17" | 25.6 | rowspan="17" | 1720 | rowspan=2 |- |Mobile || Celeron 10x0MCeleron 10x7UPentium 2117UPentium 20x0M || 350–1100 |- | rowspan="2" | HD Graphics 2500 ||Workstation || Xeon E3-1265LV2 || rowspan="2" | 0152 || rowspan="3" | 650–1150 || rowspan="15" | Yes |- | rowspan="2" | Desktop || Core i3-32x0Core i3-32x0TCore i5-3xx0Core i5-3xx0SCore i5-3xx0T |- | rowspan="12" |HD Graphics 4000 || Core i3-3225Core i3-3245Core i5-3475SCore i5-3570KCore i7-3770Core i7-3770x || rowspan="1" | 0162 || rowspan="13" | 128:16:2(GT2) |- | rowspan="11" |Mobile || Core i3-3110M || rowspan="11" | 0166 || 650–1000 |- | Core i3-3120M Core i5-3210M || 650–1100 |- | Core i3-3120ME || 650–900 |- | Core i3-3217U Core i5-3317U || 350–1050 |- | Core i3-3217UE || 350–900 |- | Core i3-3229Y Core i5-3339Y Core i5-3439Y || 350–850 |- | Core i5-33x0M || 650–1200 |- | Core i5-3337U || 350–1100 |- | Core i5-3427U || 350–1150 |- | Core i5-3610ME || 650–950 |- | Core i7-3520MCore i7-3xx7UCore i7-3xxxQMCore i7-3920XM || 350–1300 |- |HD Graphics P4000 || Workstation || Xeon E3-12x5V2 || 016A || 650–1250
Gen7.5
1 FP32 ALUs : EUs : Subslices Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions. Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.