Moore's law is the observation that the number of transistors in an integrated circuit (IC) doubles about every two years, with minimal increase in cost. Despite the name, Moore's law describes an empirical relationship, not a scientific law. This type of observation, an experience curve effect, quantifies efficiency gains from learned experience in production.
The observation is named after Gordon Moore, the co-founder of Fairchild Semiconductor and Intel and former Chief Executive Officer of the latter, who in 1965 noted that the number of components per integrated circuit had been doubling every year, and projected that this rate of growth would continue for at least another decade. In 1975, looking forward to the next decade, he revised the forecast to doubling every two years, a compound annual growth rate (CAGR) of 41%. Moore's empirical evidence did not imply that the historical trend would continue; nevertheless, his prediction has held since 1975 and has since become known as a law.
Moore's prediction has been used in the semiconductor industry to guide long-term planning and to set targets for research and development (R&D). Advancements in digital electronics, such as the reduction in quality-adjusted prices of microprocessors, the increase in memory capacity (RAM and flash), the improvement of sensors, and even the number and size of pixels in digital cameras, are strongly linked to Moore's law. These ongoing changes in digital electronics have been a driving force of technological and social change, productivity, and economic growth.
Industry experts have not reached a consensus on exactly when Moore's law will cease to apply. Microprocessor architects report that semiconductor advancement has slowed industry-wide since around 2010, slightly below the pace predicted by Moore's law. In September 2022, Nvidia CEO Jensen Huang considered Moore's law dead, while Intel's then-CEO Pat Gelsinger had the opposite view.
History In 1959, Douglas Engelbart studied the projected downscaling of integrated circuit (IC) size, publishing his results in the article "Microelectronics, and the Art of Similitude". Engelbart presented his findings at the 1960 International Solid-State Circuits Conference, where Moore was present in the audience.
In 1965, Gordon Moore, who at the time was working as the director of research and development at Fairchild Semiconductor, was asked to contribute to the thirty-fifth-anniversary issue of Electronics magazine with a prediction on the future of the semiconductor components industry over the next ten years. His response was a brief article entitled "Cramming more components onto integrated circuits". Within his editorial, he speculated that by 1975 it would be possible to contain as many as components on a single quarter-square-inch (~ ) semiconductor.
The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. Moore posited a log–linear relationship between device complexity (higher circuit density at reduced cost) and time. In a 2015 interview, Moore noted of the 1965 article: "... I just did a wild extrapolation saying it's going to continue to double every year for the next 10 years." One historian of the law cites Stigler's law of eponymy, to introduce the fact that the regular doubling of components was known to many working in the field.
In 1974, Robert H. Dennard at IBM recognized the rapid MOSFET scaling technology and formulated what became known as Dennard scaling, which describes that as MOS transistors get smaller, their power density stays constant such that the power use remains in proportion with area. Evidence from the semiconductor industry shows that this inverse relationship between power density and areal density broke down in the mid-2000s.
At the 1975 IEEE International Electron Devices Meeting, Moore revised his forecast rate, predicting semiconductor complexity would continue to double annually until about 1980, after which it would decrease to a rate of doubling approximately every two years. He outlined several contributing factors for this exponential behavior: The advent of metal–oxide–semiconductor (MOS) technology The exponential rate of increase in die sizes, coupled with a decrease in defective densities, with the result that semiconductor manufacturers could work with larger areas without losing reduction yields Finer minimum dimensions What Moore called "circuit and device cleverness" Shortly after 1975, Caltech professor Carver Mead popularized the term Moore's law.in reference to Gordon E. Moore's statements at the IEEE. Moore's law eventually came to be widely accepted as a goal for the semiconductor industry, and it was cited by competitive semiconductor manufacturers as they strove to increase processing power. Moore viewed his eponymous law as surprising and optimistic: "Moore's law is a violation of Murphy's law. Everything gets better and better." The observation was even seen as a self-fulfilling prophecy.
The doubling period is often misquoted as 18 months because of a separate prediction by Moore's colleague, Intel executive David House. In 1975, House noted that Moore's revised law of doubling transistor count every 2 years in turn implied that computer chip performance would roughly double every 18 months, with no increase in power consumption. Mathematically, Moore's law predicted that transistor count would double every 2 years due to shrinking transistor dimensions and other improvements. As a consequence of shrinking dimensions, Dennard scaling predicted that power consumption per unit area would remain constant. Combining these effects, David House deduced that computer chip performance would roughly double every 18 months. Also due to Dennard scaling, this increased performance would not be accompanied by increased power, i.e., the energy efficiency of silicon-based computer chips roughly doubles every 18 months. Dennard scaling ended in the 2000s. Koomey later showed that a similar rate of efficiency improvement predated silicon chips and Moore's law, for technologies such as vacuum tubes.
Microprocessor architects report that since around 2010, semiconductor advancement has slowed industry-wide below the pace predicted by Moore's law. Brian Krzanich, the former CEO of Intel, cited Moore's 1975 revision as a precedent for the current deceleration, which results from technical challenges and is "a natural part of the history of Moore's law". The rate of improvement in physical dimensions known as Dennard scaling also ended in the mid-2000s. As a result, much of the semiconductor industry has shifted its focus to the needs of major computing applications rather than semiconductor scaling. Nevertheless, as of 2019, leading semiconductor manufacturers TSMC and Samsung Electronics claimed to keep pace with Moore's law with 10, 7, and 5 nm nodes in mass production.
Moore's second law
As the cost of computer power to the consumer falls, the cost for producers to fulfill Moore's law follows an opposite trend: R&D, manufacturing, and test costs have increased steadily with each new generation of chips. The cost of the tools, principally extreme ultraviolet lithography (EUVL), used to manufacture chips doubles every 4 years. Rising manufacturing costs are an important consideration for the sustaining of Moore's law. This led to the formulation of Moore's second law, also called Rock's law (named after Arthur Rock), which is that the capital cost of a semiconductor fabrication plant also increases exponentially over time.
Major enabling factors
Numerous innovations by scientists and engineers have sustained Moore's law since the beginning of the IC era. Some of the key innovations are listed below, as examples of breakthroughs that have advanced integrated circuit and semiconductor device fabrication technology, allowing transistor counts to grow by more than seven orders of magnitude in less than five decades. Integrated circuit (IC): The raison d'être for Moore's law. The germanium hybrid IC was invented by Jack Kilby at Texas Instruments in 1958,Kilby, Jack, "Miniaturized electronic circuits", , issued June 23, 1964 (filed February 6, 1959). followed by the invention of the silicon monolithic IC chip by Robert Noyce at Fairchild Semiconductor in 1959.Noyce, Robert, "Semiconductor device-and-lead structure", , issued April 25, 1961 (filed July 30, 1959). Complementary metal–oxide–semiconductor (CMOS): The CMOS process was invented by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963.Wanlass, F., "Low stand-by power complementary field effect circuitry", , issued December 5, 1967 (filed June 18, 1963). Dynamic random-access memory (DRAM): DRAM was developed by Robert H. Dennard at IBM in 1967.Dennard, Robert H., "Field-effect transistor memory", , issued June 4, 1968 (filed July 14, 1967) Chemically amplified photoresist: Invented by Hiroshi Ito, C. Grant Willson and J. M. J. Fréchet at IBM circa 1980,, "Positive and Negative Working Resist Compositions with Acid-Generating Photoinitiator and Polymer with Acid-Labile Groups Pendant From Polymer Backbone" J. M. J. Fréchet, H. Ito and C. G. Willson 1985., . which was 5–10 times more sensitive to ultraviolet light. IBM introduced chemically amplified photoresist for DRAM production in the mid-1980s. Deep UV excimer laser photolithography: Invented by Kanti Jain. at IBM circa 1980. Prior to this, excimer lasers had been mainly used as research devices since their development in the 1970s.Basov, N. G. et al., Zh. Eksp. Fiz. i Tekh. Pis'ma. Red. 12, 473 (1970). From a broader scientific perspective, the invention of excimer laser lithography has been highlighted as one of the major milestones in the 50-year history of the laser. Interconnect innovations: Interconnect innovations of the late 1990s, including chemical-mechanical polishing or chemical mechanical planarization (CMP), trench isolation, and copper interconnects—although not directly a factor in creating smaller transistors—have enabled improved wafer yield, additional layers of metal wires, closer spacing of devices, and lower electrical resistance. "Table 1: 1990 enabling multilevel metallization; 1995 enabling STI compact isolation, polysilicon patterning and yield / defect reduction"
Computer industry technology roadmaps predicted in 2001 that Moore's law would continue for several generations of semiconductor chips.
Recent trends
One of the key technical challenges of engineering future nanoscale transistors is the design of gates. As device dimensions shrink, controlling the current flow in the thin channel becomes more difficult. Modern nanoscale transistors typically take the form of multi-gate MOSFETs, with the FinFET being the most common nanoscale transistor. The FinFET has gate dielectric on three sides of the channel. In comparison, the gate-all-around MOSFET (GAAFET) structure has even better gate control. A gate-all-around MOSFET (GAAFET) was first demonstrated in 1988 by a Toshiba research team led by Fujio Masuoka, who demonstrated a vertical nanowire GAAFET that he called a surrounding gate transistor (SGT). Masuoka, best known as the inventor of flash memory, later left Toshiba and founded Unisantis Electronics in 2004 to research surrounding-gate technology along with Tohoku University. In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device at the time, based on FinFET technology.