Tick–tock model

Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every new process technology was first used to manufacture a die shrink of a proven microarchitecture (tick), followed by a new microarchitecture on the now-proven process (tock). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. More generally, tick–tock is an engineering model which refreshes one half of a binary system each release cycle.

History Every "tick" represented a shrinking of the process technology of the previous microarchitecture (with minor changes, commonly to the caches, and rarely introducing new instructions, as with Broadwell in late 2014) and every "tock" designated a new microarchitecture. These occurred roughly every year to 18 months.

Due to the slowing rate of process improvements, in 2014 Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture not considered a new generation in and of itself. In March 2016, Intel announced in a Form 10-K report that it would always do this in future, deprecating the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization.

After introducing the Skylake architecture on a 14 nm process in 2015, its first optimization was Kaby Lake in 2016. Intel then announced a second optimization, Coffee Lake, in 2017 making a total of four generations at 14 nm before the Palm Cove die shrink to 10 nm in 2018.

Roadmap

Pentium 4 / Core / Xeon Roadmap

+ Pentium 4 / Core / Xeon Roadmap Change(step) Fabricationprocess Micro-architecture Code namesfor step IntelGenerationDesktop/Mobile IntelGenerationXeon Intel Microcodeshortcut(s)Desktop/WSIntel Releases Linux CPU Microcodes To fix Meltdown & Spectre Bugs by Lawrence Abrams on January 11, 2018Linux* Processor Microcode Data File Version 20180312 on 3/12/2018 Intel Microcodeshortcut(s)Xeon/Server Releasedate Processors 8P/4P Server 4P/2P Server/WS Embedded Xeon 1P Xeon Enthusiast/WS Desktop Mobile Tick(new fabrica-tion process) 65 nm P6, NetBurst Yonah (P6),Presler (NetBurst),Cedar Mill (NetBurst) colspan="4" rowspan="3" 1995-11-1 (P6),2000-11-20 (NetBurst) colspan="2" rowspan="5" rowspan="3" Presler (NetBurst) Cedar Mill (NetBurst) Yonah (P6) Tock(new micro-architecture) Core Merom 2006-07-27 Tigerton WoodcrestClovertown Kentsfield Conroe Merom Tick 45 nm Penryn 2007-11-11 Dunnington Harpertown Yorkfield Wolfdale Penryn Tock Nehalem Nehalem 1 rowspan="2" NHM rowspan="2" 2008-11-17 Beckton Gainestown Lynnfield Bloomfield Lynnfield Clarksfield Tick 32 nm Westmere 1 WSM 2010-01-04 Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale Tock Sandy Bridge Sandy Bridge 2 1 (E3/E5) SNB JKT (Jaketown) 2011-01-09 Sandy Bridge-EP Gladden Sandy Bridge Sandy Bridge-E Sandy Bridge Sandy Bridge-M Tick 22 nm Ivy Bridge 3 2 (E3/E5/E7) IVB IVT (Ivytown) 2012-04-29 Ivy Bridge-EX Ivy Bridge-EP Gladden Ivy Bridge Ivy Bridge-E Ivy Bridge Ivy Bridge-M Tock Haswell Haswell 4 3 (E3/E5/E7) HSW, CRW (Crystal Well)with Iris ProProducts formerly Crystal Well at Intel web pageWhat is Crystalwell? by Matt Egan on OCT 31, 2013 at macworld.com HSX 2013-06-02 Haswell-EX Haswell-EP Haswell-DT Haswell-E Haswell-DT Haswell-MB (notebooks)Haswell-LP (ultrabooks) Refresh Haswell Refresh,Devil's Canyon 2014-05-11,2014-06-02 colspan="5" rowspan="1" align="center" Devil's Canyon rowspan="1" align="center" Tick (Process) 14 nm Broadwell 5 4 (E3/E5/E7) BDW BDX 2014-09-05 Broadwell-EX Broadwell-EP Broadwell-DE Broadwell-DT Broadwell-E Broadwell-DT Broadwell-HBroadwell-UBroadwell-Y Tock (Architecture) Skylake Skylake 6 5 (E3)1 (SP)W-2100W-31xx SKLSKL-SSKL-XSKL-HSKL-USKL-YSKL-DSKL-DT SKX 2015-08-05 Skylake-SP Skylake-DE Skylake-D/DT/H Skylake-X Skylake Skylake-HSkylake-USkylake-Y Optimization(Refresh) Kaby Lake 7 6 (E3) KBL rowspan="5" 2017-01-03 colspan="3" Kaby Lake-DT/Hcores: 4 (4/8) Kaby Lake-X Kaby Lake Kaby Lake-HKaby Lake-UKaby Lake-Y Kaby Lake RProducts formerly Kaby Lake R 8 KBL-R 2017-08-21 colspan="6" Kaby Lake R Coffee Lake 8 E-2100 CFLCFL-SCFL-ECFL-HCFL-U 2017-10-05 colspan="2" Coffee Lake-H Coffee Lake-S WS (Coffee Lake-E) Coffee Lake-S Coffee Lake-HCoffee Lake-U Whiskey Lake,Amber Lake 8 rowspan="2" WHLAML 2018-08-28 colspan="6" Whiskey Lake-UAmber Lake-Y Skylake (Skylake-X Refresh) 9 2018-10-08 colspan="4" Skylake X colspan="2" Coffee Lake (Coffee Lake Refresh) 9 E-2200 CFL-RCFL-ERCFL-HR 2018-10-08, 2019-04-23 colspan="3" Coffee Lake-S WS (Coffee Lake-ER) Coffee Lake-R Coffee Lake-H RefreshCascade Lake 10 2 (SP)W-2200W-3200 CSL CXL 2019-04-02 Cascade Lake-SP Cascade Lake-AP Cascade Lake-WCascade Lake-X colspan="2" Comet Lake, Amber Lake 10 CMLAML 2019-08-21 colspan="4" rowspan="1" align="center" Comet Lake-W Comet Lake-S Comet Lake-HComet Lake-UAmber Lake-Y Cascade Lake (Cascade Lake Refresh) 2 (SP) 2020-02-24 Cascade Lake R colspan="5" Cooper Lake 3 (SP) CPLCPL-SP 2020-06-18 Cooper Lake-SP colspan="6" Architecture Cypress Cove Rocket Lake 11 E-2300 RKL rowspan="2" 2021-03-30 colspan="3" Rocket Lake-E Rocket Lake-W Rocket Lake-S Process 10 nm Palm Cove Cannon Lake 8 CNL 2018-05-16 colspan="6" Cannon Lake-U Architecture Sunny Cove Ice Lake 10 3 (SP) ICL ICXICL-SP 2019-08-01 Ice Lake-SP (2021-04-06) Ice Lake-D (April 2021) colspan="3" Ice Lake-UIce Lake-Y Optimization Willow Cove Tiger Lake 11 rowspan="2" TGL rowspan="2" 2020-09-02 colspan="6" Tiger Lake-H35 Tiger Lake-UP3Tiger Lake-UP4 Architecture Intel 7 Golden Cove Alder Lake 12 ADL 2021-11-04 colspan="5" align="center" Alder Lake-S Alder Lake-HXAlder Lake-HAlder Lake-PAlder Lake-U Sapphire Rapids 4 (SP)W-2400W-3400 SPR 2023-01-10 Sapphire Rapids-SP Sapphire Rapids-HBMSapphire Rapids-SP colspan="2" Sapphire Rapids-WS colspan="2" align="center" Optimization Raptor Cove Raptor Lake 13 RPL rowspan="4" 2022-10-20 colspan="5" align="center" Raptor Lake-S Raptor Lake-HXRaptor Lake-HRaptor Lake-PRaptor Lake-U Raptor Lake (Raptor Lake Refresh) 14 E-2400 RPL-R 2023-10-17 colspan="3" Raptor Lake-E Raptor Lake-S Refresh rowspan="2" 2024-01-08 rowspan="2" colspan="6" Raptor Lake-HX RefreshCore Series 1 Raptor Lake-U Refresh Emerald Rapids Xeon 5 (SP) EMR 2023-12-14 Emerald Rapids-SP colspan="5" align="center" Tick Intel 4 Redwood Cove Meteor Lake Core Ultra (Series 1) MTL 2023-12-14 colspan="5" Meteor Lake-SMeteor Lake-PS Meteor Lake-HMeteor Lake-U Tick Intel 3 Granite Rapids rowspan="3" Xeon 6 (SP) rowspan="3" GNR 2024-09-24 Granite Rapids-AP rowspan="2" rowspan="3" colspan="4" colspan="2" colspan="2" Tick TSMC N3B Lion Cove Arrow Lake 15 (informally)Core Ultra 200SCore Ultra (Series 2) rowspan="2" ARL rowspan="2" 2024-10-03 rowspan="2" colspan="5" align="center" Arrow Lake-SArrow Lake-SK Core Ultra 200HCore Ultra 200HXIntel Core Ultra H & HX Series Arrow Lake-RArrow Lake-KArrow Lake-KF Lunar Lake Core Ultra 200VCore Ultra (Series 2) LNL 2024-09-03 colspan="6" align="center" Lunar Lake-VLunar Lake-MX Change(step) Fabricationprocess Micro-architecture Code namesfor step IntelGenerationDesktop IntelGenerationXeon Intel Microcodeshortcut(s)Desktop/WS Intel Microcodeshortcut(s)Xeon/Server Releasedate8P/4P Server4P/2P Server/WSEmbedded Xeon1P XeonEnthusiast/WSDesktopMobileProcessors

Atom roadmap

With Silvermont Intel tried to start tick-tock in Atom architecture but problems with the 10 nm process prevented it.

In the table below instead of tick-tock steps process-architecture-optimization are used. There is no official confirmation that Intel uses process-architecture-optimization for Atom, but it enables us to understand what changes happened in each generation.

+ Atom roadmap Change Fabricationprocess Micro-architecture(Abbr.) Code namesfor step Releasedate Processors/SoCs MID, Smartphone Tablet Netbook Nettop Embedded Server CE Process / architecture 45 nm Bonnell (BNL) Bonnell 2008 Silverthorne Diamondville Optimization Bonnell 2010 Lincroft Pineview Tunnel CreekStellarton SodavilleGroveland Process 32 nm Saltwell 2011 Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview) Clover Trail (Cloverview) Cedar Trail (Cedarview) Centerton & Briarwood Berryville Process / architecture 22 nm Silvermont (SLM) Silvermont 2013 Merrifield (Tangier) & Moorefield (Anniedale) & Slayton Bay Trail-T(Valleyview) Bay Trail-M(Valleyview) Bay Trail-D(Valleyview) Bay Trail-I(Valleyview) AvotonRangeley Process 14 nm Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview) Braswell Denverton Architecture Goldmont(GLM) Goldmont 2016 Broxton Broxton Apollo Lake Apollo Lake Apollo Lake Denverton Architecture Goldmont Plus(GLM+, GLP) Goldmont Plus 2017 Gemini Lake Gemini Lake Gemini Lake Optimization Goldmont Plus 2019 Gemini Lake Refresh Gemini Lake Refresh Gemini Lake Refresh Process / architecture 10 nm Tremont Tremont 2020 Jasper Lake Jasper Lake Jasper Lake Elkhart Lake Snow Ridge Architecture Intel 7 Gracemont Gracemont 2021 Alder Lake & Raptor Lake (hybrid) Process / architecture Intel 4 Crestmont Crestmont 2023 Meteor Lake (hybrid) Sierra Forest-SPSierra Forest-AP

Note: There is further the Xeon Phi. It has up to now undergone four development steps with a current top model that got the code name Knights Landing (shortcut: KNL; the predecessor code names all had the leading term Knights in their name) that is derived from the Silvermont architecture as used for the Intel Atom series but realized in a shrunk 14 nm (FinFET) technology.Intel veröffentlicht Xeon Phi mit bis zu 7 Teraflops In 2018, Intel announced that Knights Landing and all further Xeon Phi CPU models were discontinued. However, Intel's Sierra Forest and subsequent Atom-based Xeon CPUs are likely a spiritual successor to Xeon Phi.

Both

Tick–tock model

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