The NEC V60 is a CISC microprocessor manufactured by NEC starting in 1986. Several improved versions were introduced with the same instruction set architecture (ISA), the V70 in 1987, and the V80 and AFPP in 1989. They were succeeded by the V800 product families, which is currently produced by Renesas Electronics.
The V60 family includes a floating-point unit (FPU) and memory management unit (MMU) and real-time operating system (RTOS) support for both Unix-based user-application-oriented systems and ITRON–based hardware-control-oriented embedded systems. They can be used in a multi-cpu lockstep fault-tolerant mechanism named FRM. Development tools included Ada certified system MV-4000, and an in-circuit emulator (ICE).
The V60/V70/V80's applications covered a wide area, including circuit switching telephone exchanges, minicomputers, aerospace guidance systems, word processors, industrial computers, and various arcade games.
Introduction
NEC V60 is a CISC processor manufactured by NEC starting in 1986. It was the first 32-bit general-purpose microprocessor commercially available in Japan.
Based on a relatively traditional design for the period, the V60 was a radical departure from NEC's previous, 16-bit V–series processor, the V20-V50, which were based on the Intel 8086 model, although the V60 had the ability to emulate the V20/V30.
According to NEC's documentation, this computer architectural change was due to the increasing demands for, and the diversity of, high-level programming languages. Such trends called for a processor with both improved performance, achieved by doubling the bus width to 32 bits, and with greater flexibility facilitated by having a large number of general-purpose registers. These were common features of RISC chips. At the time, a transition from CISC to RISC seemed to bring many benefits for emerging markets.
Today, RISC chips are common, and CISC designs—such as Intel's x86 and the 80486—which have been mainstream for several decades, internally adopt RISC features in their microarchitectures. According to Intel's Pat Gelsinger, binary backward compatibility for legacy software is more important than changing the ISA.
Overview
Instruction set The V60 ( μPD70616) retained a CISC architecture. Its manual describes their architecture as having "features of high-end mainframe and supercomputers", with a fully orthogonal instruction set that includes non-uniform-length instructions, memory-to-memory operations that include string manipulation, and complex operand-addressing schemes.
Family The V60 operates as a 32-bit processor internally, while externally providing 16-bit data, and 24-bit address, buses. In addition, the V60 has 32 32-bit general-purpose registers. Its basic architecture is used in several variants. The V70 (μPD70632), released in 1987, provides 32-bit external buses. Launched in 1989, the V80 (μPD70832) is the culmination of the series: having on-chip caches, a branch predictor, and less reliance on microcode for complex operations.
Software The operating systems developed for the V60-V80 series are generally oriented toward real-time operations. Several OSs were ported to the series, including real-time versions of Unix and ITRON.
Because the V60/V70 was used in various Japanese arcade games, their instruction set architecture is emulated in the MAME CPU simulator. The latest open-source code is available from the GitHub repository.
FRM All three processors have the FRM (Functional Redundancy Monitoring) synchronous multiple modular lockstep mechanism, which enables fault-tolerant computer systems. It requires multiple devices of the same model, one of which then operates in "master mode", while the other devices listen to the master device, in "checker mode". If two or more devices simultaneously output different results via their "fault output" pins, a majority-voting decision can be taken by external circuits. In addition, a recovery method for the mismatched instruction—either "roll-back by retry" or "roll-forward by exception"—can be selected via an external pin.
Pin Name I/O Function BMODE (FRM) Input Select the normal bus (master) mode or FRM operating (checker) mode () Output Master output requesting bus lock, i.e. freezing bus operationChecker output indicating a mismatch has been detected BFREZ Input Assertion for freezing bus operation RT/ Input Selecting input for "roll-back by retry" or "roll-forward by exception"
V60 The work on V60 processor began in 1982 with about 250 engineers under the leadership of Yoichi Yano, and the processor debuted in February 1986. It had a six-stage pipeline, built-in memory-management unit, and floating-point arithmetic. It was manufactured using a two-layer aluminum CMOS process technology, under a 1.5 μm design rule, to implement 375,000 transistors on a die. It operates at 5 V and was initially packaged in a 68-pin PGA. The first version ran at 16 MHz and attained 3.5 MIPS. Its sample price at launch was set at ¥100,000 ($588.23). It entered full-scale production in August 1986.
Sega employed this processor for most of its arcade game sets in the 1990s; both the Sega System 32 and the Sega Model 1 architectures used V60 as their main CPU. (The latter used the lower-cost μPD70615 variant, which doesn't implement V20/V30 emulation and FRM.) The V60 was also used as the main CPU in the SSV arcade architecture—so named because it was developed jointly by Seta, Sammy, and Visco. Sega originally considered using a 16 MHz V60 as the basis for its Sega Saturn console; but after receiving word that the PlayStation employed a 33.8 MHz MIPS R3000A processor, instead chose the dual-SH-2 design for the production model.
In 1988, NEC released a kit called PS98-145-HMW for Unix enthusiasts. The kit contained a V60 processor board that could be plugged into selected models of the PC-9800 computer series and a distribution of their UNIX System V port, the PC-UX/V Rel 2.0 (V60), on 15 8-inch floppy disks. The suggested retail price for this kit was 450,000 Yen. NEC-group companies themselves intensively employed the V60 processor. Their telephone circuit switcher (exchange), which was one of the first intended targets, used V60. In 1991, they expanded their word processor products line with Bungou Mini (文豪ミニ in Japanese) series 5SX, 7SX, and 7SD, which used the V60 for fast outline font processing, while the main system processor was a 16 MHz NEC V33. with "high speed outline font smoothing" TV CM In addition, V60 microcode variants were employed in NEC's MS-4100 minicomputer series, which was the fastest one in Japan at that time.
V70
The V70 (μPD70632) improved on the V60 by increasing the external buses to 32 bits, equal to the internal buses. It was also manufactured in 1.5 μm with a two-metal layer process. Its die had 385,000 transistors and was packaged in a 132-pin ceramic PGA. Its MMU had support for demand paging. Its floating-point unit was IEEE 754 compliant. The 20 MHz version attained a peak performance of 6.6 MIPS and was priced, at launch in August 1987, at ¥100,000 ($719.42). The initial production capacity was 20,000 units per month. A later report describes it as fabricated in 1.2-micrometer CMOS on a die. The V70 had a two-cycle non-pipeline (T1-T2) external bus system, whereas that of the V60 operated at 3 or 4 cycles (T1-T3/T4). Of course, the internal units were pipelined.
The V70 was used by Sega in its System Multi 32 and by Jaleco in its Mega System 32. (See the photo of the V70 mounted on the latter system's printed circuit board.)
JAXA embedded its variant of the V70, with the ITRON RX616 operating system, in the Guidance Control Computer of the H-IIA carrier rockets, in satellites such as the Akatsuki (Venus Climate Orbiter), and the Kibo International Space Station (ISS) module. The H-IIA launch vehicles were deployed domestically, in Japan, although their payloads included satellites from foreign countries. As described in JAXA's LSI (MPU/ASIC) roadmap, this V70 variant is designated "32bit MPU (H32/V70)", whose development, probably including the testing (QT) phase, was "from the middle of 1980s to early 1990s". This variant was used until its replacement, in 2013, by the HR5000 64-bit, 25 MHz microprocessor, which is based on the MIPS64-5Kf architecture, fabricated by HIREC, whose development was completed around 2011.
"Space Environment Data Acquisition" for the V70 was done at the Kibo-ISS exposed facility.
Item Part No. SEE (Single Event Effect)Monitored Item Result V70-MPU NASDA38510/92101xz SEU (Single Event Upset)SEL (Single Event Latch-up) Not observed(—2010/9/30)
V80 The V80 (μPD70832) was launched in the spring of 1989. By incorporating on-chip caches and a branch predictor, it was declared NEC's 486 by Computer Business Review. The performance of the V80 was two to four times than that of the V70, depending on application. For example, compared with V70, the V80 had a 32-bit hardware multiplier that reduced the number of cycles required to complete an integer-multiplication machine-instruction from 23 to 9. (For more detailed differences, see the hardware architecture section below.) The V80 was manufactured in a 0.8-micrometer CMOS process on a die area of , implementing 980,000 transistors. It was packaged in a 280-pin PGA, and operated at 25 and 33 MHz with claimed peak performances of 12.5 and 16.5 MIPS, respectively. The V80 had separate 1 KB on-die caches for both instructions and data. It had a 64-entry branch predictor, a 5% performance gain being attributed to it. The launch prices of the V80 were cited as equivalent to $1200 for the 33 MHz model and $960 for the 25 MHz model. Supposedly, a 45 MHz model was scheduled for 1990, but it did not materialize.
The V80, with μPD72691 co-FPP and μPD71101 simple peripheral chips, was used for an industrial computer running the RX-UX832 real-time UNIX operating system and a X11-R4-based windowing system.
AFPP (co-FPP) The Advanced Floating Point Processor (AFPP) (μPD72691) is a co-processor for floating-point arithmetic operations. The V60/V70/V80 themselves can perform floating-point arithmetic, but they are very slow because they lack hardware dedicated to such operations. In 1989, to compensate V60/V70/V80 for their fairly weak floating-point performance, NEC launched this 80-bit floating-point co-processor for 32-bit single precision, 64-bit double precision, and 80-bit extended precision operations according to IEEE 754 specifications. This chip had a performance of 6.7 MFLOPS, doing vector-matrix multiplication while operating at 20 MHz. It was fabricated using a 1.2-micrometer double-metal layer CMOS process, resulting in 433,000 transistors on an die. It was packaged in a 68-pin PGA. This co-processor connected to a V80 via a dedicated bus, to a V60 or V70 via a shared main bus, which constrained peak performance.
Hardware architecture The V60/V70/V80 shared a basic architecture. They had thirty-two 32-bit general-purpose registers, with the last three of them commonly used as stack pointer, frame pointer, and argument pointer, which well matched high level language compilers' calling conventions. The V60 and V70 have 119 machine instructions, with that number being extended slightly to 123 instructions for the V80. The instructions are of non-uniform length, between one and 22 bytes, and take two operands, both of which can be addresses in main memory. After studying the V60's reference manual, Paul Vixie described it as "a very VAX-ish arch, with a V20/V30 emulation mode (which[...] means it can run Intel 8086/8088 software)".