In semiconductor electronics fabrication technology, a self-aligned gate is a transistor manufacturing approach whereby the gate electrode of a MOSFET (metal–oxide–semiconductor field-effect transistor) is used as a mask for the doping of the source and drain regions. This technique ensures that the gate is naturally and precisely aligned to the edges of the source and drain.
The use of self-aligned gates in MOS transistors is one of the key innovations that led to the large increase in computing power in the 1970s. Self-aligned gates are still used in most modern integrated circuit processes.
Introduction IC construction
Integrated circuits (ICs, or "chips") are produced in a multi-step process that builds up multiple layers on the surface of a disk of silicon known as a "wafer". Each layer is patterned by coating the wafer in photoresist and then exposing it to ultraviolet light being shone through a stencil-like "mask". Depending on the process, the photoresist that was exposed to light either hardens or softens, and in either case, the softer parts are then washed away. The result is a microscopic pattern on the surface of the wafer where a portion of the top layer is exposed while the rest is protected under the remaining photoresist.
The wafer is then exposed to a variety of processes that add or remove materials from the portions of the wafer that are unprotected by the photoresist. In one common process, the wafer is heated to around 1000 °C and then exposed to a gas containing a doping material (commonly boron or phosphorus) that changes the electrical properties of the silicon. This allows the silicon to become an electron donor, electron receptor, or near-insulator depending on the type and/or amount of the dopant. In a typical IC this process is used to produce the individual transistors that make up the key elements of an IC.
In the MOSFET, the three parts of a transistor are the source, the drain, and the gate (see diagram). The "field effect" in the name refers to changes to the conductivity that occur when a voltage is applied to the gate. The key point is that this electric field can cause the "channel" region separating the source and drain to become the same type as the source-drain, thus turning the transistor "on". Because no current flows from the gate to the drain, the switching energy of a FET is very small compared to earlier bipolar junction transistor types where the gate (or base as it was known) was in-line with the current.
Older methodology In early MOSFET fabrication methodologies, the gate was made of aluminum which melts at 660 °C, so it had to be deposited as one of the last steps in the process after all the doping stages had been completed at around 1000 °C.
The wafer as a whole is first chosen to have a particular electrical quality as biased either positive, or "p", or negative, "n". In the illustration the base material is "p", so the channels will be made "n", which is known as n-channel or nMOS. A mask is then used to produce areas where the negative "n" sections of the transistors will be placed. The wafer is then heated to around 1000 °C, and exposed to a doping gas that diffuses into the surface of the wafer to produce the "n" sections. A thin layer of insulator material (silicon dioxide) is then grown on top of the wafer. Finally, the gate is patterned on top of the insulating layer in a new photo-lithographic operation. To ensure the gate actually overlaps the underlying source and drain, the gate material has to be wider than the gap between the n sections, typically as much as three times. This wastes space and creates extra capacitance between the gate and the source-drain. This parasitic capacitance requires that the entire chip be driven at high power levels to ensure clean switching which is inefficient. Additionally, the variation in the misalignment of the gate to the underlying source-drain means that there is high chip-to-chip variability even when they are working properly.
Self-alignment
The self-aligned gate developed in several steps to its present form. Key to the advance was the discovery that heavily doped poly-silicon was conductive enough to replace aluminum. This meant the gate layer could be created at any stage in the multi-step fabrication process.
In the self-aligned process, the key gate-insulating layer is formed near the beginning of the process. Then the gate is deposited and patterned on top. Then the source-drains are doped (for poly-silicon the gates are doped simultaneously). The source-drain pattern thus represents only the outside edges of the source and drain, the inside edge of those sections being masked by the gate itself. As a result, the source and drain "self-align" to the gate. Since they are always perfectly positioned, there is no need to make the gate wider than desired, and the parasitic capacitance is greatly reduced. Alignment time and chip-to-chip variability are likewise reduced.
After early experimentation with different gate materials using aluminum, molybdenum and amorphous silicon, the semiconductor industry almost universally adopted self-aligned gates made with polycrystalline silicon (poly-silicon), the so-called silicon-gate technology (SGT) or "self-aligned silicon-gate" technology, which had many additional benefits over the reduction of parasitic capacitances. One important feature of SGT was that the transistor was entirely buried under top quality thermal oxide (one of the best insulators known), making it possible to create new device types, not feasible with conventional technology or with self-aligned gates made with other materials. Particularly important are charge-coupled devices (CCD), used for image sensors, and non-volatile memory devices using floating silicon-gate structures. These devices dramatically enlarged the range of functionality that could be achieved with solid state electronics.
Certain innovations were required in order to make self-aligned gates:
a new process that would create the gates; a switch from amorphous silicon to polycrystalline silicon (because amorphous silicon would break where it passed over "steps" in the oxide insulating surface); a photolithography method for etching polycrystalline silicon; a method to reduce the impurities present in silicon.
Prior to these innovations, self-aligned gates had been demonstrated on metal-gate devices, but their real impact was on silicon-gate devices.
History The aluminum-gate MOS process technology started with the definition and doping of the source and drain regions of MOS transistors, followed by the gate mask that defined the thin-oxide region of the transistors. With additional processing steps, an aluminum gate would then be formed over the thin-oxide region completing the device fabrication. Due to the inevitable misalignment of the gate mask with respect to the source and drain mask, it was necessary to have a fairly large overlap area between the gate region and the source and drain regions, to ensure that the thin-oxide region would bridge the source and drain, even under worst-case misalignment. This requirement resulted in gate-to-source and gate-to-drain parasitic capacitances that were large and variable from wafer to wafer, depending on the misalignment of the gate oxide mask with respect with the source and drain mask. The result was an undesirable spread in the speed of the integrated circuits produced, and a much lower speed than theoretically possible if the parasitic capacitances could be reduced to a minimum. The overlap capacitance with the most adverse consequences on performance was the gate-to-drain parasitic capacitance, Cgd, which, by the well-known Miller effect, augmented the gate-to-source capacitance of the transistor by Cgd multiplied by the gain of the circuit to which that transistor was a part. The impact was a considerable reduction in the switching speed of transistors.
In 1966, Robert W. Bower realized that if the gate electrode was defined first, it would be possible not only to minimize the parasitic capacitances between gate and source and drain, but it would also make them insensitive to misalignment. He proposed a method in which the aluminum gate electrode itself was used as a mask to define the source and drain regions of the transistor. However, since aluminum could not withstand the high temperature required for the conventional doping of the source and drain junctions, Bower proposed to use ion implantation, a new doping technique still in development at Hughes Aircraft, his employer, and not yet available at other labs. While Bower’s idea was conceptually sound, in practice it did not work, because it was impossible to adequately passivate the transistors, and repair the radiation damage done to the silicon crystal structure by the ion implantation, since these two operations would have required temperatures in excess of the ones survivable by the aluminum gate. Thus his invention provided a proof of principle, but no commercial integrated circuit was ever produced with Bower’s method. A more refractory gate material was needed.
In 1967, John C. Sarace and collaborators at Bell Labs replaced the aluminum gate with an electrode made of vacuum-evaporated amorphous silicon and succeeded in building working self-aligned gate MOS transistors. However, the process, as described, was only a proof of principle, suitable only for the fabrication of discrete transistors and not for integrated circuits; and was not pursued any further by its investigators
In 1968, the MOS industry was prevalently using aluminum gate transistors with high threshold voltage (HVT) and desired to have a low threshold voltage (LVT) MOS process in order to increase the speed and reduce the power dissipation of MOS integrated circuits. Low threshold voltage transistors with aluminum gate demanded the use of silicon orientation, which however produced too low a threshold voltage for the parasitic MOS transistors (the MOS transistors created when aluminum over the field oxide would bridge two junctions). To increase the parasitic threshold voltage beyond the supply voltage, it was necessary to increase the N-type doping level in selected regions under the field oxide, and this was initially accomplished with the use of a so-called channel-stopper mask, and later with ion implantation.
Development of the silicon-gate technology at Fairchild The SGT was the first process technology used to fabricate commercial MOS integrated circuits that was later widely adopted by the entire industry in the 1960s. In late 1967, Tom Klein, working at the Fairchild Semiconductor R&D Labs, and reporting to Les Vadasz, realized that the work function difference between heavily P-type doped silicon and N-type silicon was 1.1 volt lower than the work function difference between aluminum and the same N-type silicon. This meant that the threshold voltage of MOS transistors with silicon gate could be 1.1 volt lower than the threshold voltage of MOS transistors with aluminum gate fabricated on the same starting material. Therefore, one could use starting material with silicon orientation and simultaneously achieve both an adequate parasitic threshold voltage and low threshold voltage transistors without the use of a channel-stopper mask or ion implantation under the field oxide. With P-type doped silicon gate it would therefore be possible not only to create self-aligned gate transistors but also a low threshold voltage process by using the same silicon orientation of the high threshold voltage process.